arm/dts/meson-gxl.dtsi

8 #include <dt-bindings/clock/gxbb-clkc.h>
24 			clocks = <&clkc CLKID_USB>;
47 		clocks = <&clkc CLKID_USB>;
58 		clocks = <&clkc CLKID_USB>;
70 		clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
82 	clocks = <&clkc CLKID_ETH>,
83 		 <&clkc CLKID_FCLK_DIV2>,
84 		 <&clkc CLKID_MPLL2>;
256 	clocks = <&clkc CLKID_HDMI_PCLK>,
257 		 <&clkc CLKID_CLK81>,
258 		 <&clkc CLKID_GCLK_VENCI_INT0>;
263 	clkc: clock-controller {  label
264 		compatible = "amlogic,gxl-clkc";
270 	clocks = <&clkc CLKID_I2C>;
274 	clocks = <&clkc CLKID_AO_I2C>;
278 	clocks = <&clkc CLKID_I2C>;
282 	clocks = <&clkc CLKID_I2C>;
676 	clocks = <&clkc CLKID_VPU>,
677 	         <&clkc CLKID_VAPB>;
685 	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
686 			  <&clkc CLKID_VPU_0>,
687 			  <&clkc CLKID_VPU>, /* Glitch free mux */
688 			  <&clkc CLKID_VAPB_0_SEL>,
689 			  <&clkc CLKID_VAPB_0>,
690 			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
691 	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
693 				 <&clkc CLKID_VPU_0>,
694 				 <&clkc CLKID_FCLK_DIV4>,
696 				 <&clkc CLKID_VAPB_0>;
708 		 <&clkc CLKID_SAR_ADC>,
709 		 <&clkc CLKID_SAR_ADC_CLK>,
710 		 <&clkc CLKID_SAR_ADC_SEL>;
715 	clocks = <&clkc CLKID_SD_EMMC_A>,
716 		 <&clkc CLKID_SD_EMMC_A_CLK0>,
717 		 <&clkc CLKID_FCLK_DIV2>;
723 	clocks = <&clkc CLKID_SD_EMMC_B>,
724 		 <&clkc CLKID_SD_EMMC_B_CLK0>,
725 		 <&clkc CLKID_FCLK_DIV2>;
731 	clocks = <&clkc CLKID_SD_EMMC_C>,
732 		 <&clkc CLKID_SD_EMMC_C_CLK0>,
733 		 <&clkc CLKID_FCLK_DIV2>;
739 	clocks = <&clkc CLKID_SPICC>;
746 	clocks = <&clkc CLKID_SPI>;
750 	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
765 	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
770 	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;