arm/dts/ls1021a.dtsi

27 		#size-cells = <0>;
32 			reg = <0xf00>;
39 			reg = <0xf01>;
70 			reg = <0x1401000 0x1000>,
71 			      <0x1402000 0x1000>,
72 			      <0x1404000 0x2000>,
73 			      <0x1406000 0x2000>;
80 			reg = <0x1530000 0x10000>;
86 			reg = <0x1ee0000 0x10000>;
92 			reg = <0x1560000 0x10000>;
94 			clock-frequency = <0>;
103 			reg = <0x1570000 0x10000>;
110 			ranges = <0x0 0x1ee1000 0x10000>;
114 				#clock-cells = <0>;
121 				reg = <0x800 0x10>;
130 				reg = <0xc00 0x10>;
135 			cluster1_clk: clk0c0@0 {
137 				#clock-cells = <0>;
138 				reg = <0x0 0x10>;
140 				clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
148 			#size-cells = <0>;
149 			reg = <0x2100000 0x10000>;
161 			#size-cells = <0>;
162 			reg = <0x2110000 0x10000>;
174 			#size-cells = <0>;
175 			reg = <0x1550000 0x10000>,
176 				<0x40000000 0x4000000>;
186 			#size-cells = <0>;
187 			reg = <0x2180000 0x10000>;
197 			#size-cells = <0>;
198 			reg = <0x2190000 0x10000>;
208 			#size-cells = <0>;
209 			reg = <0x21a0000 0x10000>;
218 			reg = <0x21c0500 0x100>;
226 			reg = <0x21c0600 0x100>;
234 			reg = <0x21d0500 0x100>;
242 			reg = <0x21d0600 0x100>;
250 			reg = <0x2950000 0x1000>;
259 			reg = <0x2960000 0x1000>;
268 			reg = <0x2970000 0x1000>;
277 			reg = <0x2980000 0x1000>;
286 			reg = <0x2990000 0x1000>;
295 			reg = <0x29a0000 0x1000>;
304 			reg = <0x2ad0000 0x10000>;
313 			reg = <0x2b50000 0x10000>;
326 			reg = <0x2b60000 0x10000>;
340 			reg = <0x2c00000 0x10000>,
341 			      <0x2c10000 0x10000>,
342 			      <0x2c20000 0x10000>;
357 			#size-cells = <0>;
358 			reg = <0x2d24000 0x4000>;
363 			reg = <0x8600000 0x1000>;
371 			reg = <0x3100000 0x10000>;
378 			reg = <0x03400000 0x20000   /* dbi registers */
379 			       0x01570000 0x10000   /* pf controls registers */
380 			       0x24000000 0x20000>; /* configuration space */
386 			bus-range = <0x0 0xff>;
387 			ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000   /* downstream I/O */
388 				  0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
393 			reg = <0x03500000 0x10000    /* dbi registers */
394 			       0x01570000 0x10000    /* pf controls registers */
395 			       0x34000000 0x20000>;  /* configuration space */
402 			bus-range = <0x0 0xff>;
403 			ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000   /* downstream I/O */
404 				  0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
409 			reg = <0x3200000 0x10000>;
410 			interrupts = <0 101 4>;