Lines Matching +full:mdio +full:- +full:mux +full:- +full:mmioreg

1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
14 enet0-rgmii-phy = &rgmii_phy1;
15 enet1-rgmii-phy = &rgmii_phy2;
16 enet2-rgmii-phy = &rgmii_phy3;
17 enet0-sgmii-phy = &sgmii_phy1c;
18 enet1-sgmii-phy = &sgmii_phy1d;
25 bus-num = <0>;
29 #address-cells = <1>;
30 #size-cells = <1>;
32 spi-max-frequency = <16000000>;
33 spi-cpol;
34 spi-cpha;
40 bus-num = <0>;
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "spi-flash";
47 spi-max-frequency = <20000000>;
55 pca9547: mux@77 {
57 #address-cells = <1>;
58 #size-cells = <0>;
61 #address-cells = <1>;
62 #size-cells = <0>;
73 #address-cells = <1>;
74 #size-cells = <0>;
80 shunt-resistor = <1000>;
86 shunt-resistor = <1000>;
91 #address-cells = <1>;
92 #size-cells = <0>;
114 #address-cells = <2>;
115 #size-cells = <1>;
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "cfi-flash";
127 bank-width = <2>;
128 device-width = <1>;
131 fpga: board-control@3,0 {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "simple-bus";
136 bank-width = <1>;
137 device-width = <1>;
140 mdio-mux-emi1 {
141 compatible = "mdio-mux-mmioreg";
142 mdio-parent-bus = <&mdio0>;
143 #address-cells = <1>;
144 #size-cells = <0>;
146 mux-mask = <0xe0>; /* EMI1[2:0] */
149 ls1021amdio0: mdio@0 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 rgmii_phy1: ethernet-phy@1 {
158 ls1021amdio1: mdio@20 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 rgmii_phy2: ethernet-phy@2 {
167 ls1021amdio2: mdio@40 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 rgmii_phy3: ethernet-phy@3 {
176 ls1021amdio3: mdio@60 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 sgmii_phy1c: ethernet-phy@1c {
185 ls1021amdio4: mdio@80 {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 sgmii_phy1d: ethernet-phy@1d {
202 tbi0: tbi-phy@8 {
204 device_type = "tbi-phy";