Lines Matching +full:0 +full:xf5000000
14 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
36 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
37 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
38 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
41 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
42 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
47 cle = <0>;
51 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
55 pinctrl-0 = <&pmx_nand>;
62 reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>;
71 ranges = <0x00000000 0xf1000000 0x0100000>;
77 reg = <0x10000 0x20>;
123 reg = <0x10030 0x4>;
130 #size-cells = <0>;
131 cell-index = <0>;
133 reg = <0x10600 0x28>;
135 pinctrl-0 = <&pmx_spi>;
144 reg = <0x10100 0x40>;
156 reg = <0x10140 0x40>;
166 reg = <0x11000 0x20>;
168 #size-cells = <0>;
172 pinctrl-0 = <&pmx_twsi0>;
179 reg = <0x12000 0x100>;
183 pinctrl-0 = <&pmx_uart0>;
190 reg = <0x12100 0x100>;
194 pinctrl-0 = <&pmx_uart1>;
201 reg = <0x20000 0x80>, <0x1500 0x20>;
206 reg = <0x20000 0x120>;
213 reg = <0x20110 0x8>;
220 reg = <0x2011c 0x4>;
221 clocks = <&core_clk 0>;
227 reg = <0x20128 0x4>;
234 reg = <0x20200 0x10>, <0x20210 0x10>;
239 reg = <0x20300 0x20>;
242 clocks = <&core_clk 0>;
247 reg = <0x20300 0x28>, <0x20108 0x4>;
256 reg = <0x30000 0x10000>;
261 marvell,crypto-sram-size = <0x800>;
267 reg = <0x50000 0x1000>;
275 reg = <0x60800 0x100
276 0x60A00 0x100>;
295 reg = <0x60900 0x100
296 0x60B00 0x100>;
316 #size-cells = <0>;
317 reg = <0x72000 0x4000>;
318 clocks = <&gate_clk 0>;
322 eth0port: ethernet0-port@0 {
324 reg = <0>;
335 #size-cells = <0>;
336 reg = <0x72004 0x84>;
338 clocks = <&gate_clk 0>;
347 #size-cells = <0>;
348 reg = <0x76000 0x4000>;
351 pinctrl-0 = <&pmx_ge1>;
355 eth1port: ethernet1-port@0 {
357 reg = <0>;
367 reg = <0x82000 0x0334>;
370 #phy-cells = <0>;
376 reg = <0x84000 0x0334>;
379 #phy-cells = <0>;
385 #sound-dai-cells = <0>;
386 reg = <0xa0000 0x2210>;