Lines Matching +full:0 +full:x2680000
35 reg = <0x80000000 0x40000000>;
42 reg = <0x02561000 0x1000>,
43 <0x02562000 0x2000>,
44 <0x02564000 0x1000>,
45 <0x02566000 0x2000>;
80 reg = <0x02310000 0x200>;
85 reg = <0x02620000 0x1000>;
90 ti,syscon-pll = <&pllctrl 0xe4>;
91 ti,syscon-dev = <&devctrl 0x328>;
92 ti,wdt-list = <0>;
102 reg = <0x02530c00 0x100>;
112 reg = <0x02531000 0x100>;
119 reg = <0x02530000 0x400>;
124 #size-cells = <0>;
129 reg = <0x02530400 0x400>;
134 #size-cells = <0>;
139 reg = <0x02530800 0x400>;
144 #size-cells = <0>;
149 reg = <0x21000400 0x200>;
151 ti,davinci-spi-intr-line = <0>;
155 #size-cells = <0>;
160 reg = <0x21000600 0x200>;
162 ti,davinci-spi-intr-line = <0>;
166 #size-cells = <0>;
171 reg = <0x21000800 0x200>;
173 ti,davinci-spi-intr-line = <0>;
177 #size-cells = <0>;
184 reg = <0x2620738 24>;
192 reg = <0x2680000 0x10000>;
203 reg = <0x2690000 0x70000>;
211 reg = <0x022f0080 0x80>;
217 reg = <0x022f0000 0x80>;
224 reg = <0x0260bf00 0x100>;
274 reg = <0x21000A00 0x00000100>;
275 ranges = <0 0 0x30000000 0x10000000
276 1 0 0x21000A00 0x00000100>;
284 ti,syscon-dev = <&devctrl 0x2a0>;
293 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
294 ranges = <0x81000000 0 0 0x23250000 0 0x4000
295 0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
302 interrupt-map-mask = <0 0 0 7>;
303 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
304 <0 0 0 2 &pcie_intc0 1>, /* INT B */
305 <0 0 0 3 &pcie_intc0 2>, /* INT C */
306 <0 0 0 4 &pcie_intc0 3>; /* INT D */