Lines Matching +full:clock +full:- +full:output +full:- +full:names
13 #clock-cells = <0>;
14 compatible = "ti,keystone,main-pll-clock";
17 reg-names = "control", "multiplier", "post-divider";
21 #clock-cells = <0>;
22 compatible = "ti,keystone,pll-clock";
24 clock-output-names = "papllclk";
26 reg-names = "control";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "ddr-3a-pll-clk";
35 reg-names = "control";
39 #clock-cells = <0>;
40 compatible = "ti,keystone,psc-clock";
42 clock-output-names = "usb1";
44 reg-names = "control", "domain";
45 domain-id = <0>;
49 #clock-cells = <0>;
50 compatible = "ti,keystone,psc-clock";
52 clock-output-names = "hyperlink-0";
54 reg-names = "control", "domain";
55 domain-id = <5>;
59 #clock-cells = <0>;
60 compatible = "ti,keystone,psc-clock";
62 clock-output-names = "pcie1";
64 reg-names = "control", "domain";
65 domain-id = <18>;
69 #clock-cells = <0>;
70 compatible = "ti,keystone,psc-clock";
72 clock-output-names = "xge";
74 reg-names = "control", "domain";
75 domain-id = <29>;