arm/dts/imx7ulp.dtsi

210 			assigned-clock-rates = <48000000>;
211 			assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
212 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
221 			assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
222 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
223 			assigned-clock-rates = <48000000>;
233 			assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
234 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
235 			assigned-clock-rates = <48000000>;
245 			assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
246 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
247 			assigned-clock-rates = <48000000>;
257 			assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
258 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
259 			assigned-clock-rates = <48000000>;
269 			assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
270 			assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
271 			assigned-clock-rates = <24000000>;
281 			assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
282 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
283 			assigned-clock-rates = <48000000>;
352 			assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
353 			assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
367 			assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
368 			assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
380 			assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
382 			assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
416 			assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
417 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
418 			assigned-clock-rates = <48000000>;
428 			assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
429 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
430 			assigned-clock-rates = <48000000>;
440 			assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
441 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
442 			assigned-clock-rates = <48000000>;
454 			assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
455 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
456 			assigned-clock-rates = <50000000>;