Lines Matching +full:0 +full:x5b
17 reg = <0x80000000 0x20000000>;
26 pinctrl-0 = <&pinctrl_gpio>;
42 pinctrl-0 = <&pinctrl_brcm_reg>;
52 pinctrl-0 = <&pinctrl_bt_reg>;
85 pinctrl-0 = <&pinctrl_i2c1>;
90 reg = <0x08>;
182 pinctrl-0 = <&pinctrl_i2c2>;
189 pinctrl-0 = <&pinctrl_i2c3>;
196 pinctrl-0 = <&pinctrl_i2c4>;
200 #sound-dai-cells = <0>;
201 reg = <0x0a>;
205 pinctrl-0 = <&pinctrl_sai1_mclk>;
213 reg = <0x60>;
219 pinctrl-0 = <&pinctrl_sai1>;
223 assigned-clock-rates = <0>, <36864000>;
229 pinctrl-0 = <&pinctrl_uart1>;
237 pinctrl-0 = <&pinctrl_uart3>;
246 pinctrl-0 = <&pinctrl_uart6>;
260 pinctrl-0 = <&pinctrl_usdhc1>;
271 pinctrl-0 = <&pinctrl_usdhc3>;
285 pinctrl-0 = <&pinctrl_wdog>;
293 MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
299 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
305 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
311 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
312 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
318 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
319 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
325 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
326 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
332 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
333 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
339 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
340 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
341 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
342 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
348 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
354 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
355 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
361 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
362 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
363 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
364 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
370 MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
371 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
377 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
378 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
379 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
380 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
381 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
382 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
383 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
389 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
390 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
391 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
392 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
393 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
394 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
395 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
396 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
397 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
398 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
399 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
405 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
406 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
407 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
408 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
409 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
410 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
411 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
412 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
413 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
414 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
415 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
421 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
422 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
423 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
424 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
425 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
426 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
427 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
428 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
429 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
430 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
431 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
439 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74