Lines Matching +full:0 +full:x5a
19 reg = <0x80000000 0x80000000>;
25 pinctrl-0 = <&pinctrl_spi1>;
27 gpio-sck = <&gpio1 13 0>;
28 gpio-mosi = <&gpio1 9 0>;
29 cs-gpios = <&gpio1 12 0>;
32 #size-cells = <0>;
34 gpio_spi: gpio_spi@0 {
38 reg = <0>;
40 registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
48 #size-cells = <0>;
50 reg_usb_otg1_vbus: regulator@0 {
52 reg = <0>;
86 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
87 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
88 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
94 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
95 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
101 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
102 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
108 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
109 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
115 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
116 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
122 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
123 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
124 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
125 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
131 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
132 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
133 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
134 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
135 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
136 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
142 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
143 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
144 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
145 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
146 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
147 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
153 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
154 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
155 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
156 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
157 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
158 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
164 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
165 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
166 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
167 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
168 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
169 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
170 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */
171 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */
177 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
178 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
179 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
180 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
181 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
182 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
188 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
189 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
190 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
191 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
192 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
193 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
199 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
200 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
201 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
202 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
203 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
204 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
205 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
206 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
207 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
208 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
209 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
215 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
216 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
217 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
218 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
219 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
220 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
221 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
222 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
223 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
224 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
225 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
231 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
232 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
233 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
234 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
235 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
236 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
237 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
238 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
239 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
240 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
241 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
250 pinctrl-0 = <&pinctrl_i2c1>;
255 reg = <0x08>;
348 pinctrl-0 = <&pinctrl_i2c2>;
355 pinctrl-0 = <&pinctrl_i2c3>;
362 pinctrl-0 = <&pinctrl_i2c4>;
368 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
371 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
381 pinctrl-0 = <&pinctrl_usdhc2>;
392 pinctrl-0 = <&pinctrl_usdhc3>;