Lines Matching +full:0 +full:x020e0000
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
85 reg = <0x00a01000 0x1000>,
86 <0x00a00100 0x100>;
92 #size-cells = <0>;
94 ckil: clock@0 {
96 reg = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
113 #clock-cells = <0>;
114 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
156 reg = <0x00900000 0x4000>;
161 reg = <0x00904000 0x1000>;
166 reg = <0x00905000 0x1B000>;
171 reg = <0x00a02000 0x1000>;
183 reg = <0x02000000 0x100000>;
190 reg = <0x02000000 0x40000>;
195 reg = <0x02004000 0x4000>;
197 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
219 reg = <0x02008000 0x4000>;
231 reg = <0x0200c000 0x4000>;
243 reg = <0x02010000 0x4000>;
255 reg = <0x02014000 0x4000>;
267 reg = <0x02018000 0x4000>;
269 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
279 reg = <0x02020000 0x4000>;
281 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
291 reg = <0x02024000 0x4000>;
293 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
303 reg = <0x02028000 0x4000>;
305 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
316 reg = <0x0202c000 0x4000>;
318 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
329 reg = <0x02030000 0x4000>;
331 dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
342 reg = <0x02034000 0x4000>;
344 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
355 reg = <0x02080000 0x4000>;
365 reg = <0x02084000 0x4000>;
375 reg = <0x02088000 0x4000>;
385 reg = <0x0208c000 0x4000>;
395 reg = <0x02098000 0x4000>;
404 reg = <0x0209c000 0x4000>;
415 reg = <0x020a0000 0x4000>;
426 reg = <0x020a4000 0x4000>;
437 reg = <0x020a8000 0x4000>;
448 reg = <0x020ac000 0x4000>;
459 reg = <0x020b0000 0x4000>;
470 reg = <0x020b8000 0x4000>;
478 reg = <0x020bc000 0x4000>;
485 reg = <0x020c0000 0x4000>;
493 reg = <0x020c4000 0x4000>;
505 reg = <0x020c8000 0x4000>;
515 anatop-reg-offset = <0x120>;
518 anatop-min-bit-val = <0>;
521 anatop-enable-bit = <0>;
537 reg = <0x020c9000 0x1000>;
547 reg = <0x020ca000 0x1000>;
555 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
556 reg = <0x020cc000 0x4000>;
559 compatible = "fsl,sec-v4.0-mon-rtc-lp";
561 offset = <0x34>;
568 offset = <0x38>;
569 mask = <0x61>;
573 compatible = "fsl,sec-v4.0-pwrkey";
582 reg = <0x020d0000 0x4000>;
587 reg = <0x020d4000 0x4000>;
593 reg = <0x020d8000 0x4000>;
601 reg = <0x020dc000 0x4000>;
606 fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
611 reg = <0x020e0000 0x4000>;
617 reg = <0x020e4000 0x4000>;
622 reg = <0x020e8000 0x4000>;
633 reg = <0x020ec000 0x4000>;
645 reg = <0x020f0000 0x4000>;
656 reg = <0x020f4000 0x4000>;
665 reg = <0x020f8000 0x4000>;
676 reg = <0x020fc000 0x4000>;
689 reg = <0x02100000 0x100000>;
695 reg = <0x02184000 0x200>;
699 fsl,usbmisc = <&usbmisc 0>;
701 ahb-burst-config = <0x0>;
702 tx-burst-size-dword = <0x10>;
703 rx-burst-size-dword = <0x10>;
710 reg = <0x02184200 0x200>;
715 ahb-burst-config = <0x0>;
716 tx-burst-size-dword = <0x10>;
717 rx-burst-size-dword = <0x10>;
725 reg = <0x02184800 0x200>;
730 reg = <0x02190000 0x4000>;
744 reg = <0x02194000 0x4000>;
758 reg = <0x02198000 0x4000>;
772 #size-cells = <0>;
774 reg = <0x021a0000 0x4000>;
782 #size-cells = <0>;
784 reg = <0x021a4000 0x4000>;
792 #size-cells = <0>;
794 reg = <0x021a8000 0x4000>;
802 reg = <0x021ac000 0x4000>;
807 reg = <0x021b0000 0x4000>;
812 reg = <0x021b4000 0x4000>;
819 reg = <0x021bc000 0x4000>;
825 reg = <0x021c0000 0x4000>;
830 snvs_gpr: snvs-gpr@0x021c4000 {
832 reg = <0x021c4000 0x10000>;
837 reg = <0x021c80000 0x10000>;
842 reg = <0x021d8000 0x4000>;
848 reg = <0x021f4000 0x4000>;
850 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;