arm/dts/imx6qp.dtsi

1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 			compatible = "mmio-sram";
12 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
16 			compatible = "mmio-sram";
18 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
21 		aips-bus@2100000 {
22 			pre1: pre@21c8000 {
23 				compatible = "fsl,imx6qp-pre";
26 				clocks = <&clks IMX6QDL_CLK_PRE0>;
27 				clock-names = "axi";
31 			pre2: pre@21c9000 {
32 				compatible = "fsl,imx6qp-pre";
35 				clocks = <&clks IMX6QDL_CLK_PRE1>;
36 				clock-names = "axi";
40 			pre3: pre@21ca000 {
41 				compatible = "fsl,imx6qp-pre";
44 				clocks = <&clks IMX6QDL_CLK_PRE2>;
45 				clock-names = "axi";
49 			pre4: pre@21cb000 {
50 				compatible = "fsl,imx6qp-pre";
53 				clocks = <&clks IMX6QDL_CLK_PRE3>;
54 				clock-names = "axi";
59 				compatible = "fsl,imx6qp-prg";
61 				clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
63 				clock-names = "ipg", "axi";
68 				compatible = "fsl,imx6qp-prg";
70 				clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
72 				clock-names = "ipg", "axi";
80 	/delete-property/interrupts-extended;
86 	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
90 	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
95 	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
100 	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
104 	clock-names = "di0_pll", "di1_pll",
110 	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
114 	compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";