Lines Matching +full:imx35 +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
16 * Also for U-Boot there must be a pre-existing /memory node.
55 compatible = "fsl,imx-ckil", "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <32768>;
61 compatible = "fsl,imx-ckih1", "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <0>;
67 compatible = "fsl,imx-osc", "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <24000000>;
74 compatible = "fsl,imx6q-tempmon";
75 interrupt-parent = <&gpc>;
78 fsl,tempmon-data = <&ocotp>;
83 #address-cells = <1>;
84 #size-cells = <0>;
85 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
89 lvds-channel@0 {
90 #address-cells = <1>;
91 #size-cells = <0>;
99 remote-endpoint = <&ipu1_di0_lvds0>;
107 remote-endpoint = <&ipu1_di1_lvds0>;
112 lvds-channel@1 {
113 #address-cells = <1>;
114 #size-cells = <0>;
122 remote-endpoint = <&ipu1_di0_lvds1>;
130 remote-endpoint = <&ipu1_di1_lvds1>;
137 compatible = "arm,cortex-a9-pmu";
138 interrupt-parent = <&gpc>;
143 #address-cells = <1>;
144 #size-cells = <1>;
145 compatible = "simple-bus";
146 interrupt-parent = <&gpc>;
149 dma_apbh: dma-apbh@110000 {
150 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
156 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
157 #dma-cells = <1>;
158 dma-channels = <4>;
162 gpmi: gpmi-nand@112000 {
163 compatible = "fsl,imx6q-gpmi-nand";
164 #address-cells = <1>;
165 #size-cells = <1>;
167 reg-names = "gpmi-nand", "bch";
169 interrupt-names = "bch";
175 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
178 dma-names = "rx-tx";
183 #address-cells = <1>;
184 #size-cells = <0>;
190 clock-names = "iahb", "isfr";
197 remote-endpoint = <&ipu1_di0_hdmi>;
205 remote-endpoint = <&ipu1_di1_hdmi>;
217 clock-names = "bus", "core", "shader";
218 power-domains = <&pd_pu>;
227 clock-names = "bus", "core";
228 power-domains = <&pd_pu>;
232 compatible = "arm,cortex-a9-twd-timer";
235 interrupt-parent = <&intc>;
239 intc: interrupt-controller@a01000 {
240 compatible = "arm,cortex-a9-gic";
241 #interrupt-cells = <3>;
242 interrupt-controller;
245 interrupt-parent = <&intc>;
248 L2: l2-cache@a02000 {
249 compatible = "arm,pl310-cache";
252 cache-unified;
253 cache-level = <2>;
254 arm,tag-latency = <4 2 3>;
255 arm,data-latency = <4 2 3>;
256 arm,shared-override;
260 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
263 reg-names = "dbi", "config";
264 #address-cells = <3>;
265 #size-cells = <2>;
267 bus-range = <0x00 0xff>;
269 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
270 num-lanes = <1>;
272 interrupt-names = "msi";
273 #interrupt-cells = <1>;
274 interrupt-map-mask = <0 0 0 0x7>;
275 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
282 clock-names = "pcie", "pcie_bus", "pcie_phy";
286 aips-bus@2000000 { /* AIPS1 */
287 compatible = "fsl,aips-bus", "simple-bus";
288 #address-cells = <1>;
289 #size-cells = <1>;
293 spba-bus@2000000 {
294 compatible = "fsl,spba-bus", "simple-bus";
295 #address-cells = <1>;
296 #size-cells = <1>;
301 compatible = "fsl,imx35-spdif";
306 dma-names = "rx", "tx";
312 clock-names = "core", "rxtx0",
321 #address-cells = <1>;
322 #size-cells = <0>;
323 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
328 clock-names = "ipg", "per";
330 dma-names = "rx", "tx";
335 #address-cells = <1>;
336 #size-cells = <0>;
337 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
342 clock-names = "ipg", "per";
344 dma-names = "rx", "tx";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
356 clock-names = "ipg", "per";
358 dma-names = "rx", "tx";
363 #address-cells = <1>;
364 #size-cells = <0>;
365 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
370 clock-names = "ipg", "per";
372 dma-names = "rx", "tx";
377 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
382 clock-names = "ipg", "per";
384 dma-names = "rx", "tx";
389 #sound-dai-cells = <0>;
390 compatible = "fsl,imx35-esai";
398 clock-names = "core", "mem", "extal", "fsys", "spba";
400 dma-names = "rx", "tx";
405 #sound-dai-cells = <0>;
406 compatible = "fsl,imx6q-ssi",
407 "fsl,imx51-ssi";
412 clock-names = "ipg", "baud";
415 dma-names = "rx", "tx";
416 fsl,fifo-depth = <15>;
421 #sound-dai-cells = <0>;
422 compatible = "fsl,imx6q-ssi",
423 "fsl,imx51-ssi";
428 clock-names = "ipg", "baud";
431 dma-names = "rx", "tx";
432 fsl,fifo-depth = <15>;
437 #sound-dai-cells = <0>;
438 compatible = "fsl,imx6q-ssi",
439 "fsl,imx51-ssi";
444 clock-names = "ipg", "baud";
447 dma-names = "rx", "tx";
448 fsl,fifo-depth = <15>;
453 compatible = "fsl,imx53-asrc";
463 clock-names = "mem", "ipg", "asrck_0",
470 dma-names = "rxa", "rxb", "rxc",
472 fsl,asrc-rate = <48000>;
473 fsl,asrc-width = <16>;
487 interrupt-names = "bit", "jpeg";
490 clock-names = "per", "ahb";
491 power-domains = <&pd_pu>;
501 #pwm-cells = <2>;
502 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
507 clock-names = "ipg", "per";
512 #pwm-cells = <2>;
513 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
518 clock-names = "ipg", "per";
523 #pwm-cells = <2>;
524 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
529 clock-names = "ipg", "per";
534 #pwm-cells = <2>;
535 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
540 clock-names = "ipg", "per";
545 compatible = "fsl,imx6q-flexcan";
550 clock-names = "ipg", "per";
555 compatible = "fsl,imx6q-flexcan";
560 clock-names = "ipg", "per";
565 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
571 clock-names = "ipg", "per", "osc_per";
574 gpio1: gpio@209c000 {
575 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
579 gpio-controller;
580 #gpio-cells = <2>;
581 interrupt-controller;
582 #interrupt-cells = <2>;
585 gpio2: gpio@20a0000 {
586 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
590 gpio-controller;
591 #gpio-cells = <2>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
596 gpio3: gpio@20a4000 {
597 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
601 gpio-controller;
602 #gpio-cells = <2>;
603 interrupt-controller;
604 #interrupt-cells = <2>;
607 gpio4: gpio@20a8000 {
608 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
612 gpio-controller;
613 #gpio-cells = <2>;
614 interrupt-controller;
615 #interrupt-cells = <2>;
618 gpio5: gpio@20ac000 {
619 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
623 gpio-controller;
624 #gpio-cells = <2>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
629 gpio6: gpio@20b0000 {
630 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
634 gpio-controller;
635 #gpio-cells = <2>;
636 interrupt-controller;
637 #interrupt-cells = <2>;
640 gpio7: gpio@20b4000 {
641 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
645 gpio-controller;
646 #gpio-cells = <2>;
647 interrupt-controller;
648 #interrupt-cells = <2>;
652 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
660 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
667 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
675 compatible = "fsl,imx6q-ccm";
679 #clock-cells = <1>;
683 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
689 regulator-1p1 {
690 compatible = "fsl,anatop-regulator";
691 regulator-name = "vdd1p1";
692 regulator-min-microvolt = <1000000>;
693 regulator-max-microvolt = <1200000>;
694 regulator-always-on;
695 anatop-reg-offset = <0x110>;
696 anatop-vol-bit-shift = <8>;
697 anatop-vol-bit-width = <5>;
698 anatop-min-bit-val = <4>;
699 anatop-min-voltage = <800000>;
700 anatop-max-voltage = <1375000>;
701 anatop-enable-bit = <0>;
704 regulator-3p0 {
705 compatible = "fsl,anatop-regulator";
706 regulator-name = "vdd3p0";
707 regulator-min-microvolt = <2800000>;
708 regulator-max-microvolt = <3150000>;
709 regulator-always-on;
710 anatop-reg-offset = <0x120>;
711 anatop-vol-bit-shift = <8>;
712 anatop-vol-bit-width = <5>;
713 anatop-min-bit-val = <0>;
714 anatop-min-voltage = <2625000>;
715 anatop-max-voltage = <3400000>;
716 anatop-enable-bit = <0>;
719 regulator-2p5 {
720 compatible = "fsl,anatop-regulator";
721 regulator-name = "vdd2p5";
722 regulator-min-microvolt = <2250000>;
723 regulator-max-microvolt = <2750000>;
724 regulator-always-on;
725 anatop-reg-offset = <0x130>;
726 anatop-vol-bit-shift = <8>;
727 anatop-vol-bit-width = <5>;
728 anatop-min-bit-val = <0>;
729 anatop-min-voltage = <2100000>;
730 anatop-max-voltage = <2875000>;
731 anatop-enable-bit = <0>;
734 reg_arm: regulator-vddcore {
735 compatible = "fsl,anatop-regulator";
736 regulator-name = "vddarm";
737 regulator-min-microvolt = <725000>;
738 regulator-max-microvolt = <1450000>;
739 regulator-always-on;
740 anatop-reg-offset = <0x140>;
741 anatop-vol-bit-shift = <0>;
742 anatop-vol-bit-width = <5>;
743 anatop-delay-reg-offset = <0x170>;
744 anatop-delay-bit-shift = <24>;
745 anatop-delay-bit-width = <2>;
746 anatop-min-bit-val = <1>;
747 anatop-min-voltage = <725000>;
748 anatop-max-voltage = <1450000>;
751 reg_pu: regulator-vddpu {
752 compatible = "fsl,anatop-regulator";
753 regulator-name = "vddpu";
754 regulator-min-microvolt = <725000>;
755 regulator-max-microvolt = <1450000>;
756 regulator-enable-ramp-delay = <150>;
757 anatop-reg-offset = <0x140>;
758 anatop-vol-bit-shift = <9>;
759 anatop-vol-bit-width = <5>;
760 anatop-delay-reg-offset = <0x170>;
761 anatop-delay-bit-shift = <26>;
762 anatop-delay-bit-width = <2>;
763 anatop-min-bit-val = <1>;
764 anatop-min-voltage = <725000>;
765 anatop-max-voltage = <1450000>;
768 reg_soc: regulator-vddsoc {
769 compatible = "fsl,anatop-regulator";
770 regulator-name = "vddsoc";
771 regulator-min-microvolt = <725000>;
772 regulator-max-microvolt = <1450000>;
773 regulator-always-on;
774 anatop-reg-offset = <0x140>;
775 anatop-vol-bit-shift = <18>;
776 anatop-vol-bit-width = <5>;
777 anatop-delay-reg-offset = <0x170>;
778 anatop-delay-bit-shift = <28>;
779 anatop-delay-bit-width = <2>;
780 anatop-min-bit-val = <1>;
781 anatop-min-voltage = <725000>;
782 anatop-max-voltage = <1450000>;
787 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
795 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
803 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
806 snvs_rtc: snvs-rtc-lp {
807 compatible = "fsl,sec-v4.0-mon-rtc-lp";
814 snvs_poweroff: snvs-poweroff {
815 compatible = "syscon-poweroff";
823 snvs_lpgpr: snvs-lpgpr {
824 compatible = "fsl,imx6q-snvs-lpgpr";
839 compatible = "fsl,imx6q-src", "fsl,imx51-src";
843 #reset-cells = <1>;
847 compatible = "fsl,imx6q-gpc";
849 interrupt-controller;
850 #interrupt-cells = <3>;
853 interrupt-parent = <&intc>;
855 clock-names = "ipg";
858 #address-cells = <1>;
859 #size-cells = <0>;
861 power-domain@0 {
863 #power-domain-cells = <0>;
865 pd_pu: power-domain@1 {
867 #power-domain-cells = <0>;
868 power-supply = <®_pu>;
879 gpr: iomuxc-gpr@20e0000 {
880 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
883 mux: mux-controller {
884 compatible = "mmio-mux";
885 #mux-control-cells = <1>;
890 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
905 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
910 clock-names = "ipg", "ahb";
911 #dma-cells = <3>;
912 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
916 aips-bus@2100000 { /* AIPS2 */
917 compatible = "fsl,aips-bus", "simple-bus";
918 #address-cells = <1>;
919 #size-cells = <1>;
924 compatible = "fsl,sec-v4.0";
925 #address-cells = <1>;
926 #size-cells = <1>;
933 clock-names = "mem", "aclk", "ipg", "emi_slow";
936 compatible = "fsl,sec-v4.0-job-ring";
942 compatible = "fsl,sec-v4.0-job-ring";
953 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
959 ahb-burst-config = <0x0>;
960 tx-burst-size-dword = <0x10>;
961 rx-burst-size-dword = <0x10>;
966 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
973 ahb-burst-config = <0x0>;
974 tx-burst-size-dword = <0x10>;
975 rx-burst-size-dword = <0x10>;
980 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
986 ahb-burst-config = <0x0>;
987 tx-burst-size-dword = <0x10>;
988 rx-burst-size-dword = <0x10>;
993 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
999 ahb-burst-config = <0x0>;
1000 tx-burst-size-dword = <0x10>;
1001 rx-burst-size-dword = <0x10>;
1006 #index-cells = <1>;
1007 compatible = "fsl,imx6q-usbmisc";
1013 compatible = "fsl,imx6q-fec";
1015 interrupt-names = "int0", "pps";
1016 interrupts-extended =
1022 clock-names = "ipg", "ahb", "ptp";
1034 compatible = "fsl,imx6q-usdhc";
1040 clock-names = "ipg", "ahb", "per";
1041 bus-width = <4>;
1046 compatible = "fsl,imx6q-usdhc";
1052 clock-names = "ipg", "ahb", "per";
1053 bus-width = <4>;
1058 compatible = "fsl,imx6q-usdhc";
1064 clock-names = "ipg", "ahb", "per";
1065 bus-width = <4>;
1070 compatible = "fsl,imx6q-usdhc";
1076 clock-names = "ipg", "ahb", "per";
1077 bus-width = <4>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1094 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1104 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1116 compatible = "fsl,imx6q-mmdc";
1125 #address-cells = <2>;
1126 #size-cells = <1>;
1127 compatible = "fsl,imx6q-weim";
1131 fsl,weim-cs-gpr = <&gpr>;
1136 compatible = "fsl,imx6q-ocotp", "syscon";
1152 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1158 compatible = "fsl,imx6-mipi-csi2";
1160 #address-cells = <1>;
1161 #size-cells = <0>;
1166 clock-names = "dphy", "ref", "pix";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1182 remote-endpoint = <&ipu1_di0_mipi>;
1190 remote-endpoint = <&ipu1_di1_mipi>;
1197 compatible = "fsl,imx6q-vdoa";
1204 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1209 clock-names = "ipg", "per";
1211 dma-names = "rx", "tx";
1216 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1221 clock-names = "ipg", "per";
1223 dma-names = "rx", "tx";
1228 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1233 clock-names = "ipg", "per";
1235 dma-names = "rx", "tx";
1240 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1245 clock-names = "ipg", "per";
1247 dma-names = "rx", "tx";
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1255 compatible = "fsl,imx6q-ipu";
1262 clock-names = "bus", "di0", "di1";
1269 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1288 remote-endpoint = <&hdmi_mux_0>;
1293 remote-endpoint = <&mipi_mux_0>;
1298 remote-endpoint = <&lvds0_mux_0>;
1303 remote-endpoint = <&lvds1_mux_0>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1318 remote-endpoint = <&hdmi_mux_1>;
1323 remote-endpoint = <&mipi_mux_1>;
1328 remote-endpoint = <&lvds0_mux_1>;
1333 remote-endpoint = <&lvds1_mux_1>;