Lines Matching +full:1 +full:a01000
10 #address-cells = <1>;
11 #size-cells = <1>;
83 #address-cells = <1>;
90 #address-cells = <1>;
103 port@1 {
104 reg = <1>;
112 lvds-channel@1 {
113 #address-cells = <1>;
115 reg = <1>;
126 port@1 {
127 reg = <1>;
143 #address-cells = <1>;
144 #size-cells = <1>;
157 #dma-cells = <1>;
164 #address-cells = <1>;
165 #size-cells = <1>;
183 #address-cells = <1>;
201 port@1 {
202 reg = <1>;
234 interrupts = <1 13 0xf01>;
239 intc: interrupt-controller@a01000 {
259 pcie: pcie@1ffc000 {
270 num-lanes = <1>;
273 #interrupt-cells = <1>;
275 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
288 #address-cells = <1>;
289 #size-cells = <1>;
295 #address-cells = <1>;
296 #size-cells = <1>;
321 #address-cells = <1>;
329 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
335 #address-cells = <1>;
343 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
349 #address-cells = <1>;
357 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
363 #address-cells = <1>;
371 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
413 dmas = <&sdma 37 1 0>,
414 <&sdma 38 1 0>;
429 dmas = <&sdma 41 1 0>,
430 <&sdma 42 1 0>;
445 dmas = <&sdma 45 1 0>,
446 <&sdma 46 1 0>;
468 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
469 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
492 resets = <&src 1>;
679 #clock-cells = <1>;
689 regulator-1p1 {
746 anatop-min-bit-val = <1>;
763 anatop-min-bit-val = <1>;
780 anatop-min-bit-val = <1>;
843 #reset-cells = <1>;
858 #address-cells = <1>;
865 pd_pu: power-domain@1 {
866 reg = <1>;
885 #mux-control-cells = <1>;
918 #address-cells = <1>;
919 #size-cells = <1>;
925 #address-cells = <1>;
926 #size-cells = <1>;
971 fsl,usbmisc = <&usbmisc 1>;
1006 #index-cells = <1>;
1082 #address-cells = <1>;
1092 #address-cells = <1>;
1102 #address-cells = <1>;
1126 #size-cells = <1>;
1160 #address-cells = <1>;
1175 #address-cells = <1>;
1186 port@1 {
1187 reg = <1>;
1253 #address-cells = <1>;
1273 ipu1_csi1: port@1 {
1274 reg = <1>;
1278 #address-cells = <1>;
1286 ipu1_di0_hdmi: endpoint@1 {
1287 reg = <1>;
1308 #address-cells = <1>;
1316 ipu1_di1_hdmi: endpoint@1 {
1317 reg = <1>;