arm/dts/imx6q.dtsi

1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 		#address-cells = <1>;
17 		#size-cells = <0>;
20 			compatible = "arm,cortex-a9";
23 			next-level-cache = <&L2>;
24 			operating-points = <
32 			fsl,soc-operating-points = <
33 				/* ARM kHz  SOC-PU uV */
40 			clock-latency = <61036>; /* two CLK32 periods */
41 			#cooling-cells = <2>;
47 			clock-names = "arm", "pll2_pfd2_396m", "step",
49 			arm-supply = <&reg_arm>;
50 			pu-supply = <&reg_pu>;
51 			soc-supply = <&reg_soc>;
55 			compatible = "arm,cortex-a9";
58 			next-level-cache = <&L2>;
59 			operating-points = <
67 			fsl,soc-operating-points = <
68 				/* ARM kHz  SOC-PU uV */
75 			clock-latency = <61036>; /* two CLK32 periods */
81 			clock-names = "arm", "pll2_pfd2_396m", "step",
83 			arm-supply = <&reg_arm>;
84 			pu-supply = <&reg_pu>;
85 			soc-supply = <&reg_soc>;
89 			compatible = "arm,cortex-a9";
92 			next-level-cache = <&L2>;
93 			operating-points = <
101 			fsl,soc-operating-points = <
102 				/* ARM kHz  SOC-PU uV */
109 			clock-latency = <61036>; /* two CLK32 periods */
115 			clock-names = "arm", "pll2_pfd2_396m", "step",
117 			arm-supply = <&reg_arm>;
118 			pu-supply = <&reg_pu>;
119 			soc-supply = <&reg_soc>;
123 			compatible = "arm,cortex-a9";
126 			next-level-cache = <&L2>;
127 			operating-points = <
135 			fsl,soc-operating-points = <
136 				/* ARM kHz  SOC-PU uV */
143 			clock-latency = <61036>; /* two CLK32 periods */
149 			clock-names = "arm", "pll2_pfd2_396m", "step",
151 			arm-supply = <&reg_arm>;
152 			pu-supply = <&reg_pu>;
153 			soc-supply = <&reg_soc>;
158 		ocram: sram@900000 {
159 			compatible = "mmio-sram";
164 		aips-bus@2000000 { /* AIPS1 */
165 			spba-bus@2000000 {
167 					#address-cells = <1>;
168 					#size-cells = <0>;
169 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
174 					clock-names = "ipg", "per";
176 					dma-names = "rx", "tx";
182 				compatible = "fsl,imx6q-iomuxc";
187 			compatible = "fsl,imx6q-ahci";
193 			clock-names = "sata", "sata_ref", "ahb";
203 			clock-names = "bus", "core";
204 			power-domains = <&pd_pu>;
208 			#address-cells = <1>;
209 			#size-cells = <0>;
210 			compatible = "fsl,imx6q-ipu";
217 			clock-names = "bus", "di0", "di1";
224 					remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
232 					remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
245 					remote-endpoint = <&hdmi_mux_2>;
250 					remote-endpoint = <&mipi_mux_2>;
255 					remote-endpoint = <&lvds0_mux_2>;
260 					remote-endpoint = <&lvds1_mux_2>;
269 					remote-endpoint = <&hdmi_mux_3>;
274 					remote-endpoint = <&mipi_mux_3>;
279 					remote-endpoint = <&lvds0_mux_3>;
284 					remote-endpoint = <&lvds1_mux_3>;
290 	capture-subsystem {
291 		compatible = "fsl,imx-capture-subsystem";
295 	display-subsystem {
296 		compatible = "fsl,imx-display-subsystem";
302 	gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
311 	gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
316 	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
320 	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
324 	gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
329 	gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
335 	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
340 		compatible = "video-mux";
341 		mux-controls = <&mux 0>;
342 		#address-cells = <1>;
343 		#size-cells = <0>;
349 				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
364 				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
370 		compatible = "video-mux";
371 		mux-controls = <&mux 1>;
372 		#address-cells = <1>;
373 		#size-cells = <0>;
379 				remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
394 				remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
401 	compatible = "fsl,imx6q-hdmi";
407 			remote-endpoint = <&ipu2_di0_hdmi>;
415 			remote-endpoint = <&ipu2_di1_hdmi>;
422 		remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
431 	clock-names = "di0_pll", "di1_pll",
435 	lvds-channel@0 {
440 				remote-endpoint = <&ipu2_di0_lvds0>;
448 				remote-endpoint = <&ipu2_di1_lvds0>;
453 	lvds-channel@1 {
458 				remote-endpoint = <&ipu2_di0_lvds1>;
466 				remote-endpoint = <&ipu2_di1_lvds1>;
477 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
485 			remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
493 			remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
501 			remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
512 				remote-endpoint = <&ipu2_di0_mipi>;
520 				remote-endpoint = <&ipu2_di1_mipi>;
527 	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
537 	compatible = "fsl,imx6q-vpu", "cnm,coda960";