arm/dts/imx6dl.dtsi

1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 		#address-cells = <1>;
16 		#size-cells = <0>;
19 			compatible = "arm,cortex-a9";
22 			next-level-cache = <&L2>;
23 			operating-points = <
29 			fsl,soc-operating-points = <
30 				/* ARM kHz  SOC-PU uV */
35 			clock-latency = <61036>; /* two CLK32 periods */
36 			#cooling-cells = <2>;
42 			clock-names = "arm", "pll2_pfd2_396m", "step",
44 			arm-supply = <&reg_arm>;
45 			pu-supply = <&reg_pu>;
46 			soc-supply = <&reg_soc>;
50 			compatible = "arm,cortex-a9";
53 			next-level-cache = <&L2>;
54 			operating-points = <
60 			fsl,soc-operating-points = <
61 				/* ARM kHz  SOC-PU uV */
66 			clock-latency = <61036>; /* two CLK32 periods */
72 			clock-names = "arm", "pll2_pfd2_396m", "step",
74 			arm-supply = <&reg_arm>;
75 			pu-supply = <&reg_pu>;
76 			soc-supply = <&reg_soc>;
82 			compatible = "mmio-sram";
87 		aips1: aips-bus@2000000 {
89 				compatible = "fsl,imx6dl-iomuxc";
103 		aips2: aips-bus@2100000 {
105 				#address-cells = <1>;
106 				#size-cells = <0>;
107 				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
116 	capture-subsystem {
117 		compatible = "fsl,imx-capture-subsystem";
121 	display-subsystem {
122 		compatible = "fsl,imx-display-subsystem";
128 	gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
138 	gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
146 	gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
151 	gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
159 	gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
166 	gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
175 	gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
182 		compatible = "video-mux";
183 		mux-controls = <&mux 0>;
184 		#address-cells = <1>;
185 		#size-cells = <0>;
191 				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
199 				remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
207 				remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
215 				remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
230 				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
236 		compatible = "video-mux";
237 		mux-controls = <&mux 1>;
238 		#address-cells = <1>;
239 		#size-cells = <0>;
245 				remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
253 				remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
261 				remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
269 				remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
284 				remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
291 	compatible = "fsl,imx6dl-gpt";
295 	compatible = "fsl,imx6dl-hdmi";
300 		remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
308 	clock-names = "di0_pll", "di1_pll",
316 		#address-cells = <1>;
317 		#size-cells = <0>;
321 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
326 			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
332 		#address-cells = <1>;
333 		#size-cells = <0>;
337 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
342 			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
348 		#address-cells = <1>;
349 		#size-cells = <0>;
353 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
358 			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
364 		#address-cells = <1>;
365 		#size-cells = <0>;
369 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
374 			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
379 &mux {
380 	mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
390 	compatible = "fsl,imx6dl-vpu", "cnm,coda960";