Lines Matching +full:hix5hd2 +full:- +full:clock
4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 * SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/clock/histb-clock.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/ti-syscon.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "arm,psci-0.2";
28 #address-cells = <2>;
29 #size-cells = <0>;
32 compatible = "arm,cortex-a53";
35 enable-method = "psci";
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
46 compatible = "arm,cortex-a53";
49 enable-method = "psci";
53 compatible = "arm,cortex-a53";
56 enable-method = "psci";
60 gic: interrupt-controller@f1001000 {
61 compatible = "arm,gic-400";
64 #address-cells = <0>;
65 #interrupt-cells = <3>;
66 interrupt-controller;
70 compatible = "arm,armv8-timer";
82 compatible = "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
87 crg: clock-reset-controller@8a22000 {
88 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
90 #clock-cells = <1>;
91 #reset-cells = <2>;
93 gmacphyrst: reset-controller {
94 compatible = "ti,syscon-reset";
95 #reset-cells = <1>;
96 ti,reset-bits =
104 sysctrl: system-controller@8000000 {
105 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
107 #clock-cells = <1>;
108 #reset-cells = <2>;
111 perictrl: peripheral-controller@8a20000 {
112 compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
113 "simple-mfd";
115 #address-cells = <1>;
116 #size-cells = <1>;
119 usb2_phy1: usb2-phy@120 {
120 compatible = "hisilicon,hi3798cv200-usb2-phy";
124 #address-cells = <1>;
125 #size-cells = <0>;
129 #phy-cells = <0>;
135 #phy-cells = <0>;
140 usb2_phy2: usb2-phy@124 {
141 compatible = "hisilicon,hi3798cv200-usb2-phy";
145 #address-cells = <1>;
146 #size-cells = <0>;
150 #phy-cells = <0>;
156 compatible = "hisilicon,hi3798cv200-combphy";
158 #phy-cells = <1>;
161 assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
162 assigned-clock-rates = <100000000>;
163 hisilicon,fixed-mode = <PHY_TYPE_USB3>;
167 compatible = "hisilicon,hi3798cv200-combphy";
169 #phy-cells = <1>;
172 assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
173 assigned-clock-rates = <100000000>;
174 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
179 compatible = "pinconf-single";
181 pinctrl-single,register-width = <32>;
182 pinctrl-single,function-mask = <7>;
183 pinctrl-single,gpio-range = <
213 range: gpio-range {
214 #pinctrl-single,gpio-range-cells = <3>;
223 clock-names = "apb_pclk";
232 clock-names = "apb_pclk";
237 compatible = "hisilicon,hix5hd2-i2c";
239 #address-cells = <1>;
240 #size-cells = <0>;
242 clock-frequency = <400000>;
248 compatible = "hisilicon,hix5hd2-i2c";
250 #address-cells = <1>;
251 #size-cells = <0>;
253 clock-frequency = <400000>;
259 compatible = "hisilicon,hix5hd2-i2c";
261 #address-cells = <1>;
262 #size-cells = <0>;
264 clock-frequency = <400000>;
270 compatible = "hisilicon,hix5hd2-i2c";
272 #address-cells = <1>;
273 #size-cells = <0>;
275 clock-frequency = <400000>;
281 compatible = "hisilicon,hix5hd2-i2c";
283 #address-cells = <1>;
284 #size-cells = <0>;
286 clock-frequency = <400000>;
295 num-cs = <1>;
296 cs-gpios = <&gpio7 1 0>;
298 clock-names = "apb_pclk";
299 #address-cells = <1>;
300 #size-cells = <0>;
305 compatible = "snps,dw-mshc";
310 clock-names = "ciu", "biu";
312 reset-names = "reset";
317 compatible = "hisilicon,hi3798cv200-dw-mshc";
324 clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
326 reset-names = "reset";
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 gpio-ranges = <&pmx0 0 0 8>;
340 clock-names = "apb_pclk";
348 gpio-controller;
349 #gpio-cells = <2>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 gpio-ranges = <
360 clock-names = "apb_pclk";
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
374 clock-names = "apb_pclk";
382 gpio-controller;
383 #gpio-cells = <2>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 gpio-ranges = <
393 clock-names = "apb_pclk";
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
407 clock-names = "apb_pclk";
415 gpio-controller;
416 #gpio-cells = <2>;
417 interrupt-controller;
418 #interrupt-cells = <2>;
420 clock-names = "apb_pclk";
428 gpio-controller;
429 #gpio-cells = <2>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
434 clock-names = "apb_pclk";
442 gpio-controller;
443 #gpio-cells = <2>;
444 interrupt-controller;
445 #interrupt-cells = <2>;
446 gpio-ranges = <&pmx0 0 46 8>;
448 clock-names = "apb_pclk";
456 gpio-controller;
457 #gpio-cells = <2>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
460 gpio-ranges = <&pmx0 0 54 8>;
462 clock-names = "apb_pclk";
470 gpio-controller;
471 #gpio-cells = <2>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
476 clock-names = "apb_pclk";
484 gpio-controller;
485 #gpio-cells = <2>;
486 interrupt-controller;
487 #interrupt-cells = <2>;
488 gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
490 clock-names = "apb_pclk";
498 gpio-controller;
499 #gpio-cells = <2>;
500 interrupt-controller;
501 #interrupt-cells = <2>;
502 gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
504 clock-names = "apb_pclk";
512 gpio-controller;
513 #gpio-cells = <2>;
514 interrupt-controller;
515 #interrupt-cells = <2>;
516 gpio-ranges = <&pmx0 0 88 8>;
518 clock-names = "apb_pclk";
523 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
529 clock-names = "mac_core", "mac_ifc";
533 reset-names = "mac_core", "mac_ifc", "phy";
538 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
544 clock-names = "mac_core", "mac_ifc";
548 reset-names = "mac_core", "mac_ifc", "phy";
553 compatible = "hisilicon,hix5hd2-ir";
561 compatible = "hisilicon,hi3798cv200-pcie";
565 reg-names = "control", "rc-dbi", "config";
566 #address-cells = <3>;
567 #size-cells = <2>;
569 bus-range = <0 15>;
570 num-lanes = <1>;
574 interrupt-names = "msi";
575 #interrupt-cells = <1>;
576 interrupt-map-mask = <0 0 0 0>;
577 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
582 clock-names = "aux", "pipe", "sys", "bus";
584 reset-names = "soft", "sys", "bus";
586 phy-names = "phy";
591 compatible = "generic-ohci";
597 clock-names = "bus", "clk12", "clk48";
599 reset-names = "bus";
601 phy-names = "usb";
606 compatible = "generic-ehci";
612 clock-names = "bus", "phy", "utmi";
616 reset-names = "bus", "phy", "utmi";
618 phy-names = "usb";