Lines Matching +full:0 +full:x03600000
16 reg = <0x00000000 0x80000000 0 0x80000000>;
22 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
23 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
26 interrupts = <1 9 0x4>;
31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
40 reg = <0x0 0x21c0500 0x0 0x100>;
41 clock-frequency = <0>; /* Updated by bootloader */
42 interrupts = <0 32 0x1>; /* edge triggered */
48 reg = <0x0 0x21c0600 0x0 0x100>;
49 clock-frequency = <0>; /* Updated by bootloader */
50 interrupts = <0 32 0x1>; /* edge triggered */
55 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
56 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
62 #size-cells = <0>;
63 reg = <0x0 0x2100000 0x0 0x10000>;
64 interrupts = <0 26 0x4>; /* Level high type */
71 #size-cells = <0>;
72 reg = <0x0 0x20c0000 0x0 0x10000>,
73 <0x0 0x20000000 0x0 0x10000000>;
78 esdhc: esdhc@0 {
80 reg = <0x0 0x2140000 0x0 0x10000>;
81 interrupts = <0 28 0x4>; /* Level high type */
88 reg = <0x0 0x3100000 0x0 0x10000>;
89 interrupts = <0 80 0x4>; /* Level high type */
95 reg = <0x0 0x3110000 0x0 0x10000>;
96 interrupts = <0 81 0x4>; /* Level high type */
102 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
103 0x00 0x03480000 0x0 0x80000 /* lut registers */
104 0x10 0x00000000 0x0 0x20000>; /* configuration space */
110 bus-range = <0x0 0xff>;
111 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
112 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
117 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
118 0x00 0x03580000 0x0 0x80000 /* lut registers */
119 0x12 0x00000000 0x0 0x20000>; /* configuration space */
125 bus-range = <0x0 0xff>;
126 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
127 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
132 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
133 0x00 0x03680000 0x0 0x80000 /* lut registers */
134 0x14 0x00000000 0x0 0x20000>; /* configuration space */
140 bus-range = <0x0 0xff>;
141 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
142 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
147 reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
148 0x00 0x03780000 0x0 0x80000 /* lut registers */
149 0x16 0x00000000 0x0 0x20000>; /* configuration space */
155 bus-range = <0x0 0xff>;
156 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
157 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
162 reg = <0x0 0x3200000 0x0 0x10000>;
163 interrupts = <0 133 0x4>; /* Level high type */