Lines Matching +full:0 +full:x40000000
16 reg = <0x00000000 0x80000000 0 0x80000000>;
22 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
23 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
26 interrupts = <1 9 0x4>;
31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
40 reg = <0x0 0x21c0500 0x0 0x100>;
41 clock-frequency = <0>; /* Updated by bootloader */
42 interrupts = <0 32 0x1>; /* edge triggered */
48 reg = <0x0 0x21c0600 0x0 0x100>;
49 clock-frequency = <0>; /* Updated by bootloader */
50 interrupts = <0 32 0x1>; /* edge triggered */
55 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
56 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
62 #size-cells = <0>;
63 reg = <0x0 0x2100000 0x0 0x10000>;
64 interrupts = <0 26 0x4>; /* Level high type */
71 #size-cells = <0>;
72 reg = <0x0 0x20c0000 0x0 0x10000>,
73 <0x0 0x20000000 0x0 0x10000000>;
80 reg = <0x0 0x2140000 0x0 0x10000>;
81 interrupts = <0 28 0x4>; /* Level high type */
88 reg = <0x0 0x2240000 0x0 0x20000>;
89 interrupts = <0 21 0x4>; /* Level high type */
94 reg = <0x0 0x3100000 0x0 0x10000>;
95 interrupts = <0 80 0x4>; /* Level high type */
101 reg = <0x0 0x3110000 0x0 0x10000>;
102 interrupts = <0 81 0x4>; /* Level high type */
108 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
109 0x00 0x03480000 0x0 0x80000 /* lut registers */
110 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
111 0x20 0x00000000 0x0 0x20000>; /* configuration space */
117 bus-range = <0x0 0xff>;
118 ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
119 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
124 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
125 0x00 0x03580000 0x0 0x80000 /* lut registers */
126 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
127 0x28 0x00000000 0x0 0x20000>; /* configuration space */
133 bus-range = <0x0 0xff>;
134 ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
135 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
140 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
141 0x00 0x03680000 0x0 0x80000 /* lut registers */
142 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
143 0x30 0x00000000 0x0 0x20000>; /* configuration space */
149 bus-range = <0x0 0xff>;
150 ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
151 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
156 reg = <0x0 0x3200000 0x0 0x10000>;
157 interrupts = <0 133 4>;