Lines Matching +full:pcie +full:- +full:x4
1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
14 interrupt-parent = <&gic>;
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
25 #interrupt-cells = <3>;
26 interrupt-controller;
35 compatible = "simple-bus";
36 #address-cells = <2>;
37 #size-cells = <2>;
41 compatible = "fsl,ls1046a-clockgen";
43 #clock-cells = <2>;
48 compatible = "fsl,vf610-dspi";
49 #address-cells = <1>;
50 #size-cells = <0>;
52 interrupts = <0 64 0x4>;
53 clock-names = "dspi";
55 num-cs = <6>;
56 big-endian;
61 compatible = "fsl,vf610-dspi";
62 #address-cells = <1>;
63 #size-cells = <0>;
65 interrupts = <0 65 0x4>;
66 clock-names = "dspi";
68 num-cs = <6>;
69 big-endian;
76 interrupts = <0 62 0x4>;
77 big-endian;
78 bus-width = <4>;
82 compatible = "fsl,ifc", "simple-bus";
84 interrupts = <0 43 0x4>;
88 compatible = "fsl,vf610-i2c";
89 #address-cells = <1>;
90 #size-cells = <0>;
92 interrupts = <0 56 0x4>;
93 clock-names = "i2c";
99 compatible = "fsl,vf610-i2c";
100 #address-cells = <1>;
101 #size-cells = <0>;
103 interrupts = <0 57 0x4>;
104 clock-names = "i2c";
110 compatible = "fsl,vf610-i2c";
111 #address-cells = <1>;
112 #size-cells = <0>;
114 interrupts = <0 58 0x4>;
115 clock-names = "i2c";
121 compatible = "fsl,vf610-i2c";
122 #address-cells = <1>;
123 #size-cells = <0>;
125 interrupts = <0 59 0x4>;
126 clock-names = "i2c";
134 interrupts = <0 54 0x4>;
141 interrupts = <0 54 0x4>;
148 interrupts = <0 55 0x4>;
155 interrupts = <0 55 0x4>;
160 compatible = "fsl,ls1021a-lpuart";
162 interrupts = <0 48 0x4>;
164 clock-names = "ipg";
169 compatible = "fsl,ls1021a-lpuart";
171 interrupts = <0 49 0x4>;
173 clock-names = "ipg";
178 compatible = "fsl,ls1021a-lpuart";
180 interrupts = <0 50 0x4>;
182 clock-names = "ipg";
187 compatible = "fsl,ls1021a-lpuart";
189 interrupts = <0 51 0x4>;
191 clock-names = "ipg";
196 compatible = "fsl,ls1021a-lpuart";
198 interrupts = <0 52 0x4>;
200 clock-names = "ipg";
205 compatible = "fsl,ls1021a-lpuart";
207 interrupts = <0 53 0x4>;
209 clock-names = "ipg";
214 compatible = "fsl,vf610-qspi";
215 #address-cells = <1>;
216 #size-cells = <0>;
219 reg-names = "QuadSPI", "QuadSPI-memory";
220 num-cs = <4>;
221 big-endian;
226 compatible = "fsl,layerscape-dwc3";
233 compatible = "fsl,layerscape-dwc3";
240 compatible = "fsl,layerscape-dwc3";
246 pcie@3400000 {
247 compatible = "fsl,ls-pcie", "snps,dw-pcie";
252 reg-names = "dbi", "lut", "ctrl", "config";
253 big-endian;
254 #address-cells = <3>;
255 #size-cells = <2>;
257 bus-range = <0x0 0xff>;
259 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
262 pcie@3500000 {
263 compatible = "fsl,ls-pcie", "snps,dw-pcie";
268 reg-names = "dbi", "lut", "ctrl", "config";
269 big-endian;
270 #address-cells = <3>;
271 #size-cells = <2>;
273 num-lanes = <2>;
274 bus-range = <0x0 0xff>;
276 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
279 pcie@3600000 {
280 compatible = "fsl,ls-pcie", "snps,dw-pcie";
285 reg-names = "dbi", "lut", "ctrl", "config";
286 big-endian;
287 #address-cells = <3>;
288 #size-cells = <2>;
290 bus-range = <0x0 0xff>;
292 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
296 compatible = "fsl,ls1046a-ahci";