Lines Matching +full:0 +full:x40000000
18 #clock-cells = <0>;
27 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
28 <0x0 0x1402000 0 0x2000>, /* GICC */
29 <0x0 0x1404000 0 0x2000>, /* GICH */
30 <0x0 0x1406000 0 0x2000>; /* GICV */
31 interrupts = <1 9 0xf08>;
42 reg = <0x0 0x1ee1000 0x0 0x1000>;
50 #size-cells = <0>;
51 reg = <0x0 0x2100000 0x0 0x10000>;
52 interrupts = <0 64 0x4>;
54 clocks = <&clockgen 4 0>;
63 #size-cells = <0>;
64 reg = <0x0 0x2110000 0x0 0x10000>;
65 interrupts = <0 65 0x4>;
67 clocks = <&clockgen 4 0>;
75 reg = <0x0 0x1560000 0x0 0x10000>;
76 interrupts = <0 62 0x4>;
83 reg = <0x0 0x1530000 0x0 0x10000>;
84 interrupts = <0 43 0x4>;
90 #size-cells = <0>;
91 reg = <0x0 0x2180000 0x0 0x10000>;
92 interrupts = <0 56 0x4>;
94 clocks = <&clockgen 4 0>;
101 #size-cells = <0>;
102 reg = <0x0 0x2190000 0x0 0x10000>;
103 interrupts = <0 57 0x4>;
105 clocks = <&clockgen 4 0>;
112 #size-cells = <0>;
113 reg = <0x0 0x21a0000 0x0 0x10000>;
114 interrupts = <0 58 0x4>;
116 clocks = <&clockgen 4 0>;
123 #size-cells = <0>;
124 reg = <0x0 0x21b0000 0x0 0x10000>;
125 interrupts = <0 59 0x4>;
127 clocks = <&clockgen 4 0>;
133 reg = <0x00 0x21c0500 0x0 0x100>;
134 interrupts = <0 54 0x4>;
135 clocks = <&clockgen 4 0>;
140 reg = <0x00 0x21c0600 0x0 0x100>;
141 interrupts = <0 54 0x4>;
142 clocks = <&clockgen 4 0>;
147 reg = <0x0 0x21d0500 0x0 0x100>;
148 interrupts = <0 55 0x4>;
149 clocks = <&clockgen 4 0>;
154 reg = <0x0 0x21d0600 0x0 0x100>;
155 interrupts = <0 55 0x4>;
156 clocks = <&clockgen 4 0>;
161 reg = <0x0 0x2950000 0x0 0x1000>;
162 interrupts = <0 48 0x4>;
170 reg = <0x0 0x2960000 0x0 0x1000>;
171 interrupts = <0 49 0x4>;
179 reg = <0x0 0x2970000 0x0 0x1000>;
180 interrupts = <0 50 0x4>;
188 reg = <0x0 0x2980000 0x0 0x1000>;
189 interrupts = <0 51 0x4>;
197 reg = <0x0 0x2990000 0x0 0x1000>;
198 interrupts = <0 52 0x4>;
206 reg = <0x0 0x29a0000 0x0 0x1000>;
207 interrupts = <0 53 0x4>;
215 #size-cells = <0>;
216 reg = <0x0 0x1550000 0x0 0x10000>,
217 <0x0 0x40000000 0x0 0x4000000>;
226 reg = <0x0 0x2f00000 0x0 0x10000>;
227 interrupts = <0 60 0x4>;
233 reg = <0x0 0x3000000 0x0 0x10000>;
234 interrupts = <0 61 0x4>;
240 reg = <0x0 0x3100000 0x0 0x10000>;
241 interrupts = <0 63 0x4>;
247 reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
248 0x00 0x03410000 0x0 0x10000 /* lut registers */
249 0x40 0x00000000 0x0 0x20000>; /* configuration space */
255 bus-range = <0x0 0xff>;
256 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
257 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
262 reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
263 0x00 0x03510000 0x0 0x10000 /* lut registers */
264 0x48 0x00000000 0x0 0x20000>; /* configuration space */
271 bus-range = <0x0 0xff>;
272 ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
273 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
278 reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
279 0x00 0x03610000 0x0 0x10000 /* lut registers */
280 0x50 0x00000000 0x0 0x20000>; /* configuration space */
286 bus-range = <0x0 0xff>;
287 ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
288 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
293 reg = <0x0 0x3200000 0x0 0x10000>;
294 interrupts = <0 69 4>;
295 clocks = <&clockgen 4 0>;