Lines Matching +full:0 +full:xf08
14 #clock-cells = <0>;
23 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
24 <0x0 0x1402000 0 0x2000>, /* GICC */
25 <0x0 0x1404000 0 0x2000>, /* GICH */
26 <0x0 0x1406000 0 0x2000>; /* GICV */
27 interrupts = <1 9 0xf08>;
38 reg = <0x0 0x1ee1000 0x0 0x1000>;
46 #size-cells = <0>;
47 reg = <0x0 0x2100000 0x0 0x10000>;
48 interrupts = <0 64 0x4>;
50 clocks = <&clockgen 4 0>;
58 reg = <0x0 0x1560000 0x0 0x10000>;
59 interrupts = <0 62 0x4>;
66 reg = <0x0 0x1580000 0x0 0x10000>;
67 interrupts = <0 65 0x4>;
76 #size-cells = <0>;
77 reg = <0x0 0x2180000 0x0 0x10000>;
78 interrupts = <0 56 0x4>;
80 clocks = <&clockgen 4 0>;
87 #size-cells = <0>;
88 reg = <0x0 0x2190000 0x0 0x10000>;
89 interrupts = <0 57 0x4>;
91 clocks = <&clockgen 4 0>;
97 reg = <0x00 0x21c0500 0x0 0x100>;
98 interrupts = <0 54 0x4>;
99 clocks = <&clockgen 4 0>;
104 reg = <0x00 0x21c0600 0x0 0x100>;
105 interrupts = <0 54 0x4>;
106 clocks = <&clockgen 4 0>;
112 #size-cells = <0>;
113 reg = <0x0 0x1550000 0x0 0x10000>,
114 <0x0 0x40000000 0x0 0x4000000>;
123 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
124 0x00 0x03480000 0x0 0x40000 /* lut registers */
125 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
126 0x40 0x00000000 0x0 0x20000>; /* configuration space */
132 bus-range = <0x0 0xff>;
133 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
134 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
139 reg = <0x0 0x3200000 0x0 0x10000>;
140 interrupts = <0 69 4>;
141 clocks = <&clockgen 4 0>;
147 reg = <0x0 0x8600000 0x0 0x1000>;
148 interrupts = <0 139 0x4>;
155 reg = <0x0 0x2f00000 0x0 0x10000>;
156 interrupts = <0 61 0x4>;