arm/dts/fsl-imx8dx.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "fsl-imx8-ca35.dtsi"
8 #include <dt-bindings/soc/imx_rsrc.h>
9 #include <dt-bindings/soc/imx8_pd.h>
10 #include <dt-bindings/clock/imx8qxp-clock.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
13 #include <dt-bindings/gpio/gpio.h>
17 	compatible = "fsl,imx8dx", "fsl,imx8qxp";
18 	interrupt-parent = <&gic>;
19 	#address-cells = <2>;
20 	#size-cells = <2>;
38 		      /* DRAM space - 1, size : 1 GB DRAM */
41 	reserved-memory {
42 		#address-cells = <2>;
43 		#size-cells = <2>;
47 		 * reserved-memory layout
53 			no-map;
57 			no-map;
61 			no-map;
65 			no-map;
69 			no-map;
73 			no-map;
77 			no-map;
82 			compatible = "shared-dma-pool";
85 			alloc-ranges = <0 0x96000000 0 0x28000000>;
86 			linux,cma-default;
90 	gic: interrupt-controller@51a00000 {
91 		compatible = "arm,gic-v3";
94 		#interrupt-cells = <3>;
95 		interrupt-controller;
98 		interrupt-parent = <&gic>;
102 		compatible = "fsl,imx8-mu";
105 		interrupt-parent = <&gic>;
109 			compatible = "fsl,imx8qxp-clk";
110 			#clock-cells = <1>;
114 			compatible = "fsl,imx8qxp-iomuxc";
118 	imx8qx-pm {
119 		compatible = "simple-bus";
120 		#address-cells = <1>;
121 		#size-cells = <0>;
124 			compatible = "nxp,imx8-pd";
126 			#power-domain-cells = <0>;
127 			#address-cells = <1>;
128 			#size-cells = <0>;
132 				#power-domain-cells = <0>;
133 				power-domains = <&pd_lsio>;
137 				#power-domain-cells = <0>;
138 				power-domains = <&pd_lsio>;
142 				#power-domain-cells = <0>;
143 				power-domains = <&pd_lsio>;
147 				#power-domain-cells = <0>;
148 				power-domains = <&pd_lsio>;
152 				#power-domain-cells = <0>;
153 				power-domains = <&pd_lsio>;
157 				#power-domain-cells = <0>;
158 				power-domains = <&pd_lsio>;
162 				#power-domain-cells = <0>;
163 				power-domains = <&pd_lsio>;
167 				#power-domain-cells = <0>;
168 				power-domains = <&pd_lsio>;
173 			compatible = "nxp,imx8-pd";
175 			#power-domain-cells = <0>;
176 			#address-cells = <1>;
177 			#size-cells = <0>;
181 				#power-domain-cells = <0>;
182 				power-domains = <&pd_conn>;
186 				#power-domain-cells = <0>;
187 				power-domains = <&pd_conn>;
191 				#power-domain-cells = <0>;
192 				power-domains = <&pd_conn>;
196 				#power-domain-cells = <0>;
197 				power-domains = <&pd_conn>;
201 				#power-domain-cells = <0>;
202 				power-domains = <&pd_conn>;
207 			compatible = "nxp,imx8-pd";
209 			#power-domain-cells = <0>;
210 			#address-cells = <1>;
211 			#size-cells = <0>;
215 				#power-domain-cells = <0>;
216 				power-domains = <&pd_dma>;
220 				#power-domain-cells = <0>;
221 				power-domains = <&pd_dma>;
225 				#power-domain-cells = <0>;
226 				power-domains = <&pd_dma>;
230 				#power-domain-cells = <0>;
231 				power-domains = <&pd_dma>;
235 				#power-domain-cells = <0>;
236 				power-domains = <&pd_dma>;
237 				wakeup-irq = <225>;
243 		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
246 		interrupt-parent = <&gic>;
248 		clock-names = "per";
249 		assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
250 		assigned-clock-rates = <24000000>;
251 		power-domains = <&pd_dma_lpi2c0>;
252 		#address-cells = <1>;
253 		#size-cells = <0>;
258 		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
261 		interrupt-parent = <&gic>;
264 		clock-names = "per", "ipg";
265 		assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
266 		assigned-clock-rates = <24000000>;
267 		power-domains = <&pd_dma_lpi2c1>;
268 		#address-cells = <1>;
269 		#size-cells = <0>;
274 		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
277 		interrupt-parent = <&gic>;
279 		clock-names = "per";
280 		assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
281 		assigned-clock-rates = <24000000>;
282 		power-domains = <&pd_dma_lpi2c2>;
283 		#address-cells = <1>;
284 		#size-cells = <0>;
289 		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
292 		interrupt-parent = <&gic>;
295 		clock-names = "per", "ipg";
296 		assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
297 		assigned-clock-rates = <24000000>;
298 		power-domains = <&pd_dma_lpi2c3>;
299 		#address-cells = <1>;
300 		#size-cells = <0>;
305 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
308 		gpio-controller;
309 		#gpio-cells = <2>;
310 		power-domains = <&pd_lsio_gpio0>;
311 		interrupt-controller;
312 		#interrupt-cells = <2>;
316 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
319 		gpio-controller;
320 		#gpio-cells = <2>;
321 		power-domains = <&pd_lsio_gpio1>;
322 		interrupt-controller;
323 		#interrupt-cells = <2>;
327 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
330 		gpio-controller;
331 		#gpio-cells = <2>;
332 		power-domains = <&pd_lsio_gpio2>;
333 		interrupt-controller;
334 		#interrupt-cells = <2>;
338 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
341 		gpio-controller;
342 		#gpio-cells = <2>;
343 		power-domains = <&pd_lsio_gpio3>;
344 		interrupt-controller;
345 		#interrupt-cells = <2>;
349 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
352 		gpio-controller;
353 		#gpio-cells = <2>;
354 		power-domains = <&pd_lsio_gpio4>;
355 		interrupt-controller;
356 		#interrupt-cells = <2>;
360 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
363 		gpio-controller;
364 		#gpio-cells = <2>;
365 		power-domains = <&pd_lsio_gpio5>;
366 		interrupt-controller;
367 		#interrupt-cells = <2>;
371 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
374 		gpio-controller;
375 		#gpio-cells = <2>;
376 		power-domains = <&pd_lsio_gpio6>;
377 		interrupt-controller;
378 		#interrupt-cells = <2>;
382 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
385 		gpio-controller;
386 		#gpio-cells = <2>;
387 		power-domains = <&pd_lsio_gpio7>;
388 		interrupt-controller;
389 		#interrupt-cells = <2>;
393 		compatible = "fsl,imx8qm-lpuart";
398 		clock-names = "per", "ipg";
399 		assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
400 		assigned-clock-rates = <80000000>;
401 		power-domains = <&pd_dma_lpuart0>;
406 		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
407 		interrupt-parent = <&gic>;
413 		clock-names = "ipg", "per", "ahb";
414 		assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
415 		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
416 		assigned-clock-rates = <0>, <400000000>;
417 		power-domains = <&pd_conn_sdch0>;
418 		fsl,tuning-start-tap = <20>;
419 		fsl,tuning-step= <2>;
424 		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
425 		interrupt-parent = <&gic>;
431 		clock-names = "ipg", "per", "ahb";
432 		assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
433 		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
434 		assigned-clock-rates = <0>, <200000000>;
435 		power-domains = <&pd_conn_sdch1>;
436 		fsl,tuning-start-tap = <20>;
437 		fsl,tuning-step= <2>;
442 		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
443 		interrupt-parent = <&gic>;
449 		clock-names = "ipg", "per", "ahb";
450 		assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
451 		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
452 		assigned-clock-rates = <0>, <200000000>;
453 		power-domains = <&pd_conn_sdch2>;
458 		compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
466 		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
467 		assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
468 		assigned-clock-rates = <125000000>, <125000000>;
469 		fsl,num-tx-queues=<3>;
470 		fsl,num-rx-queues=<3>;
471 		power-domains = <&pd_conn_enet0>;
476 		compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
484 		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
485 		assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
486 		assigned-clock-rates = <125000000>, <125000000>;
487 		fsl,num-tx-queues=<3>;
488 		fsl,num-rx-queues=<3>;
489 		power-domains = <&pd_conn_enet1>;
498 /delete-node/ &A35_2;
499 /delete-node/ &A35_3;