Lines Matching full:assigned
249 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
250 assigned-clock-rates = <24000000>;
265 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
266 assigned-clock-rates = <24000000>;
280 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
281 assigned-clock-rates = <24000000>;
296 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
297 assigned-clock-rates = <24000000>;
399 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
400 assigned-clock-rates = <80000000>;
414 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
415 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
416 assigned-clock-rates = <0>, <400000000>;
432 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
433 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
434 assigned-clock-rates = <0>, <200000000>;
450 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
451 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
452 assigned-clock-rates = <0>, <200000000>;
467 assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
468 assigned-clock-rates = <125000000>, <125000000>;
485 assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
486 assigned-clock-rates = <125000000>, <125000000>;