arm/dts/exynos4.dtsi

27 		reg = <0x10440000 0x1000>;
34 		cpu-offset = <0x4000>;
35 		reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
40 		reg = <0x13800000 0x3c>;
41 		id = <0>;
46 		reg = <0x13810000 0x3c>;
52 		reg = <0x13820000 0x3c>;
58 		reg = <0x13830000 0x3c>;
64 		reg = <0x13840000 0x3c>;
70 		#size-cells = <0>;
72 		reg = <0x13860000 0x100>;
74 		interrupts = <0 56 0>;
79 		#size-cells = <0>;
81 		reg = <0x13870000 0x100>;
83 		interrupts = <1 57 0>;
88 		#size-cells = <0>;
90 		reg = <0x13880000 0x100>;
92 		interrupts = <2 58 0>;
97 		#size-cells = <0>;
99 		reg = <0x13890000 0x100>;
101 		interrupts = <3 59 0>;
106 		#size-cells = <0>;
108 		reg = <0x138a0000 0x100>;
110 		interrupts = <4 60 0>;
115 		#size-cells = <0>;
117 		reg = <0x138b0000 0x100>;
119 		interrupts = <5 61 0>;
124 		#size-cells = <0>;
126 		reg = <0x138c0000 0x100>;
128 		interrupts = <6 62 0>;
133 		#size-cells = <0>;
135 		reg = <0x138d0000 0x100>;
137 		interrupts = <7 63 0>;
142 		#size-cells = <0>;
144 		reg = <0x12510000 0x1000>;
146 		interrupts = <0 75 0>;
152 		#size-cells = <0>;
154 		reg = <0x12520000 0x1000>;
156 		interrupts = <0 76 0>;
162 		#size-cells = <0>;
164 		reg = <0x12530000 0x1000>;
166 		interrupts = <0 77 0>;
172 		#size-cells = <0>;
174 		reg = <0x12540000 0x1000>;
176 		interrupts = <0 78 0>;
182 		#size-cells = <0>;
184 		reg = <0x12550000 0x1000>;
186 		interrupts = <0 131 0>;