Lines Matching +full:0 +full:x3700
29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
63 reg = <0x44000000 0x10000>;
71 reg = <0x48180000 0x4000>;
75 #size-cells = <0>;
84 reg = <0x48140000 0x21000>;
88 ranges = <0 0x48140000 0x21000>;
92 reg = <0x800 0x50a>;
95 pinctrl-single,function-mask = <0xf>;
101 reg = <0x600 0x110>;
104 ranges = <0 0x600 0x110>;
108 reg = <0x20 0x8>;
112 #phy-cells = <0>;
118 reg = <0x28 0x8>;
122 #phy-cells = <0>;
137 reg = <0x49000000 0x10000>,
138 <0x44e10f90 0x40>;
146 reg = <0x48080000 0x2000>;
154 reg = <0x48032000 0x1000>;
166 reg = <0x4804c000 0x1000>;
177 reg = <0x50000000 0x2000>;
194 reg = <0x48028000 0x1000>;
196 #size-cells = <0>;
205 reg = <0x4802a000 0x1000>;
207 #size-cells = <0>;
217 reg = <0x48200000 0x1000>;
222 reg = <0x480c0000 0x1000>;
229 reg = <0x480c8000 0x2000>;
236 ti,mbox-tx = <3 0 0>;
237 ti,mbox-rx = <0 0 0>;
243 reg = <0x480ca000 0x2000>;
251 #size-cells = <0>;
252 reg = <0x4a100800 0x100>;
255 phy0: ethernet-phy@0 {
266 reg = <0x4a100000 0x800
267 0x4a100900 0x3700>;
270 ti,davinci-ctrl-reg-offset = <0>;
271 ti,davinci-ctrl-mod-reg-offset = <0x900>;
272 ti,davinci-ctrl-ram-offset = <0x2000>;
273 ti,davinci-ctrl-ram-size = <0x2000>;
281 reg = <0x4a120000 0x4000>;
284 ti,davinci-ctrl-reg-offset = <0>;
285 ti,davinci-ctrl-mod-reg-offset = <0x900>;
286 ti,davinci-ctrl-ram-offset = <0x2000>;
287 ti,davinci-ctrl-ram-size = <0x2000>;
294 reg = <0x48030000 0x1000>;
296 #size-cells = <0>;
310 reg = <0x48060000 0x11000>;
319 reg = <0x4802e000 0x2000>;
327 reg = <0x48040000 0x2000>;
334 reg = <0x48042000 0x2000>;
341 reg = <0x48044000 0x2000>;
349 reg = <0x48046000 0x2000>;
357 reg = <0x48048000 0x2000>;
365 reg = <0x4804a000 0x2000>;
374 reg = <0x48020000 0x2000>;
384 reg = <0x48022000 0x2000>;
394 reg = <0x48024000 0x2000>;
404 reg = <0x47401000 0x400000>;
412 reg = <0x47401400 0x400
413 0x47401000 0x200>;
418 interface-type = <0>;
426 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
427 &cppi41dma 2 0 &cppi41dma 3 0
428 &cppi41dma 4 0 &cppi41dma 5 0
429 &cppi41dma 6 0 &cppi41dma 7 0
430 &cppi41dma 8 0 &cppi41dma 9 0
431 &cppi41dma 10 0 &cppi41dma 11 0
432 &cppi41dma 12 0 &cppi41dma 13 0
433 &cppi41dma 14 0 &cppi41dma 0 1
452 reg = <0x47401c00 0x400
453 0x47401800 0x200>;
458 interface-type = <0>;
466 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
467 &cppi41dma 17 0 &cppi41dma 18 0
468 &cppi41dma 19 0 &cppi41dma 20 0
469 &cppi41dma 21 0 &cppi41dma 22 0
470 &cppi41dma 23 0 &cppi41dma 24 0
471 &cppi41dma 25 0 &cppi41dma 26 0
472 &cppi41dma 27 0 &cppi41dma 28 0
473 &cppi41dma 29 0 &cppi41dma 15 1
492 reg = <0x47400000 0x1000
493 0x47402000 0x1000
494 0x47403000 0x1000
495 0x47404000 0x4000>;
508 reg = <0x480c2000 0x1000>;
509 interrupts = <0>;