Lines Matching +full:0 +full:xc3000000
25 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
26 reg = <0xc0000000 0x08000000>;
36 reg = <0xc3000000 0x1000000>;
89 #size-cells = <0>;
93 #size-cells = <0>;
95 port@0 {
96 reg = <0>;
136 0x00 0x00101010 0x00f0f0f0
138 0x04 0x00000110 0x00000ff0
144 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
145 0x1c 0x10110010 0xf0ff00f0
147 * EMA_D[0], EMA_D[1], EMA_D[2],
151 0x24 0x11111111 0xffffffff
157 0x20 0x11111111 0xffffffff
159 0x30 0x01100000 0x0ff00000
166 pinctrl-0 = <&serial2_rxtx_pins>;
193 pinctrl-0 = <&mdio_pins>;
200 pinctrl-0 = <&mii_pins>;
208 pinctrl-0 = <&mmc0_pins>;
215 pinctrl-0 = <&i2c0_pins>;
220 #sound-dai-cells = <0>;
222 reg = <0x18>;
228 #sound-dai-cells = <0>;
230 pinctrl-0 = <&mcasp0_pins>;
233 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
235 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
236 0 0 0 0
237 0 0 0 0
238 0 0 0 0
239 0 1 2 0
259 pinctrl-0 = <&nand_pins>;
269 nand@2000000,0 {
273 reg = <0 0x02000000 0x02000000
274 1 0x00000000 0x00008000>;
277 ti,davinci-mask-ale = <0>;
278 ti,davinci-mask-cle = <0>;
279 ti,davinci-mask-chipsel = <0>;
289 * to NAND block 1 (NAND block 0 is not used by default)".
291 * "Updated NAND boot mode to offer boot from block 0 or block 1".
301 partition@0 {
303 reg = <0 0x020000>;
308 reg = <0x020000 0x080000>;
312 reg = <0x0a0000 0>;
330 pinctrl-0 = <&lcd_pins>;
341 pinctrl-0 = <&vpif_capture_pins>;