Lines Matching +full:0 +full:x7e400000
9 /memreserve/ 0x00000000 0x00001000;
29 polling-delay-passive = <0>;
37 hysteresis = <0>;
54 reg = <0x7e003000 0x1000>;
55 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
65 reg = <0x7e007000 0xf00>;
101 brcm,dma-channel-mask = <0x7f35>;
106 reg = <0x7e00b200 0x200>;
113 reg = <0x7e100000 0x28>;
119 reg = <0x7e101000 0x2000>;
126 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
127 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
132 reg = <0x7e104000 0x10>;
137 reg = <0x7e00b880 0x40>;
138 interrupts = <0 1>;
139 #mbox-cells = <0>;
144 reg = <0x7e200000 0xb4>;
173 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
223 brcm,pins = <0 1>;
374 reg = <0x7e201000 0x1000>;
379 arm,primecell-periphid = <0x00241011>;
384 reg = <0x7e202000 0x100>;
394 reg = <0x7e203000 0x20>,
395 <0x7e101098 0x02>;
405 reg = <0x7e204000 0x1000>;
409 #size-cells = <0>;
415 reg = <0x7e205000 0x1000>;
419 #size-cells = <0>;
425 reg = <0x7e206000 0x100>;
431 reg = <0x7e207000 0x100>;
437 reg = <0x7e209000 0x78>;
440 #size-cells = <0>;
456 reg = <0x7e212000 0x8>;
458 #thermal-sensor-cells = <0>;
462 aux: aux@0x7e215000 {
465 reg = <0x7e215000 0x8>;
471 reg = <0x7e215040 0x40>;
479 reg = <0x7e215080 0x40>;
483 #size-cells = <0>;
489 reg = <0x7e2150c0 0x40>;
493 #size-cells = <0>;
499 reg = <0x7e20c000 0x28>;
509 reg = <0x7e300000 0x100>;
517 reg = <0x7e400000 0x6000>;
523 reg = <0x7e700000 0x8c>;
526 #size-cells = <0>;
543 reg = <0x7e804000 0x1000>;
547 #size-cells = <0>;
553 reg = <0x7e805000 0x1000>;
557 #size-cells = <0>;
563 reg = <0x7e806000 0x1000>;
571 reg = <0x7e807000 0x100>;
577 reg = <0x7e902000 0x600>,
578 <0x7e808000 0x100>;
591 reg = <0x7e980000 0x10000>;
594 #size-cells = <0>;
603 reg = <0x7ec00000 0x1000>;
615 #size-cells = <0>;
621 #clock-cells = <0>;
629 #clock-cells = <0>;