Lines Matching +full:0 +full:xfff7c000
51 reg = <0x70000000 0x10000000>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
69 #clock-cells = <0>;
76 reg = <0x00300000 0x10000>;
97 reg = <0xfffff000 0x200>;
103 reg = <0xffffe400 0x200>;
110 reg = <0xffffe600 0x200>;
117 reg = <0xfffffc00 0x100>;
121 #size-cells = <0>;
127 #clock-cells = <0>;
134 #clock-cells = <0>;
138 plla: pllack@0 {
140 #clock-cells = <0>;
143 reg = <0>;
146 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
147 695000000 750000000 1 0
148 645000000 700000000 2 0
149 595000000 650000000 3 0
150 545000000 600000000 0 1
158 #clock-cells = <0>;
164 #clock-cells = <0>;
171 #clock-cells = <0>;
174 atmel,clk-output-range = <0 133333333>;
181 #clock-cells = <0>;
188 #size-cells = <0>;
192 prog0: prog@0 {
193 #clock-cells = <0>;
194 reg = <0>;
195 interrupts = <AT91_PMC_PCKRDY(0)>;
199 #clock-cells = <0>;
208 #size-cells = <0>;
211 #clock-cells = <0>;
217 #clock-cells = <0>;
223 #clock-cells = <0>;
229 #clock-cells = <0>;
238 #size-cells = <0>;
242 #clock-cells = <0>;
247 #clock-cells = <0>;
252 #clock-cells = <0>;
257 #clock-cells = <0>;
262 #clock-cells = <0>;
267 #clock-cells = <0>;
272 #clock-cells = <0>;
277 #clock-cells = <0>;
282 #clock-cells = <0>;
287 #clock-cells = <0>;
292 #clock-cells = <0>;
297 #clock-cells = <0>;
302 #clock-cells = <0>;
307 #clock-cells = <0>;
312 #clock-cells = <0>;
317 #clock-cells = <0>;
322 #clock-cells = <0>;
327 #clock-cells = <0>;
332 #clock-cells = <0>;
337 #clock-cells = <0>;
342 #clock-cells = <0>;
347 #clock-cells = <0>;
352 #clock-cells = <0>;
357 #clock-cells = <0>;
362 #clock-cells = <0>;
367 #clock-cells = <0>;
372 #clock-cells = <0>;
377 #clock-cells = <0>;
382 #clock-cells = <0>;
390 reg = <0xfffffd00 0x10>;
396 reg = <0xfffffd30 0xf>;
404 reg = <0xfffffd10 0x10>;
410 reg = <0xfff7c000 0x100>;
411 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
418 reg = <0xfffd4000 0x100>;
419 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
426 reg = <0xffffec00 0x200>;
427 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
437 ranges = <0xfffff200 0xfffff200 0xa00>;
438 reg = <0xfffff200 0x200
439 0xfffff400 0x200
440 0xfffff600 0x200
441 0xfffff800 0x200
442 0xfffffa00 0x200
448 0xffffffff 0xffc003ff /* pioA */
449 0xffffffff 0x800f8f00 /* pioB */
450 0xffffffff 0x00000e00 /* pioC */
451 0xffffffff 0xff0c1381 /* pioD */
452 0xffffffff 0x81ffff81 /* pioE */
488 pinctrl_dbgu: dbgu-0 {
496 pinctrl_i2c0: i2c0-0 {
504 pinctrl_i2c1: i2c1-0 {
512 pinctrl_isi_data_0_7: isi-0-data-0-7 {
527 pinctrl_isi_data_8_9: isi-0-data-8-9 {
533 pinctrl_isi_data_10_11: isi-0-data-10-11 {
541 pinctrl_usart0: usart0-0 {
547 pinctrl_usart0_rts: usart0_rts-0 {
552 pinctrl_usart0_cts: usart0_cts-0 {
559 pinctrl_usart1: usart1-0 {
565 pinctrl_usart1_rts: usart1_rts-0 {
570 pinctrl_usart1_cts: usart1_cts-0 {
577 pinctrl_usart2: usart2-0 {
583 pinctrl_usart2_rts: usart2_rts-0 {
588 pinctrl_usart2_cts: usart2_cts-0 {
595 pinctrl_usart3: usart3-0 {
601 pinctrl_usart3_rts: usart3_rts-0 {
606 pinctrl_usart3_cts: usart3_cts-0 {
613 pinctrl_nand: nand-0 {
621 pinctrl_macb_rmii: macb_rmii-0 {
635 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
649 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
651 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
656 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
663 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
673 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
680 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
687 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
697 pinctrl_ssc0_tx: ssc0_tx-0 {
699 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
704 pinctrl_ssc0_rx: ssc0_rx-0 {
713 pinctrl_ssc1_tx: ssc1_tx-0 {
720 pinctrl_ssc1_rx: ssc1_rx-0 {
729 pinctrl_spi0: spi0-0 {
731 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
738 pinctrl_spi1: spi1-0 {
747 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
751 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
755 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
759 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
763 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
767 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
771 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
775 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
779 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
785 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
786 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
789 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
793 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
797 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
801 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
805 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
809 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
813 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
817 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
823 pinctrl_fb: fb-0 {
825 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
861 reg = <0xfffff200 0x200>;
872 reg = <0xfffff400 0x200>;
883 reg = <0xfffff600 0x200>;
894 reg = <0xfffff800 0x200>;
905 reg = <0xfffffa00 0x200>;
916 reg = <0xffffee00 0x200>;
919 pinctrl-0 = <&pinctrl_dbgu>;
927 reg = <0xfff8c000 0x200>;
932 pinctrl-0 = <&pinctrl_usart0>;
940 reg = <0xfff90000 0x200>;
945 pinctrl-0 = <&pinctrl_usart1>;
953 reg = <0xfff94000 0x200>;
958 pinctrl-0 = <&pinctrl_usart2>;
966 reg = <0xfff98000 0x200>;
971 pinctrl-0 = <&pinctrl_usart3>;
979 reg = <0xfffbc000 0x100>;
982 pinctrl-0 = <&pinctrl_macb_rmii>;
990 reg = <0xfffcc000 0x100>;
991 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
997 reg = <0xfff84000 0x100>;
1000 pinctrl-0 = <&pinctrl_i2c0>;
1002 #size-cells = <0>;
1009 reg = <0xfff88000 0x100>;
1012 pinctrl-0 = <&pinctrl_i2c1>;
1014 #size-cells = <0>;
1021 reg = <0xfff9c000 0x4000>;
1024 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
1032 reg = <0xfffa0000 0x4000>;
1035 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1043 reg = <0xfffb0000 0x100>;
1044 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
1047 atmel,adc-channels-used = <0xff>;
1056 trigger-value = <0x1>;
1061 trigger-value = <0x2>;
1067 trigger-value = <0x3>;
1073 trigger-value = <0x6>;
1079 reg = <0xfffb4000 0x4000>;
1088 reg = <0xfffb8000 0x300>;
1097 reg = <0xfff80000 0x600>;
1098 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1100 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
1103 #size-cells = <0>;
1111 reg = <0xfffd0000 0x600>;
1112 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
1117 #size-cells = <0>;
1125 reg = <0xfffffd40 0x10>;
1136 #size-cells = <0>;
1138 reg = <0xfffa4000 0x200>;
1141 pinctrl-0 = <&pinctrl_spi0>;
1149 #size-cells = <0>;
1151 reg = <0xfffa8000 0x200>;
1154 pinctrl-0 = <&pinctrl_spi1>;
1162 #size-cells = <0>;
1164 reg = <0x00600000 0x80000
1165 0xfff78000 0x400>;
1166 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1171 ep@0 {
1172 reg = <0>;
1226 reg = <0xfffffd50 0x4>;
1230 #clock-cells = <0>;
1237 #clock-cells = <0>;
1245 #clock-cells = <0>;
1252 reg = <0xfffffd20 0x10>;
1260 reg = <0xfffffdb0 0x30>;
1268 reg = <0xfffffd60 0x10>;
1273 fb0: fb@0x00500000 {
1275 reg = <0x00500000 0x1000>;
1278 pinctrl-0 = <&pinctrl_fb>;
1288 reg = <0x40000000 0x10000000
1289 0xffffe200 0x200
1295 pinctrl-0 = <&pinctrl_nand>;
1298 0
1305 reg = <0x00700000 0x100000>;
1314 reg = <0x00800000 0x100000>;
1322 i2c-gpio-0 {
1331 #size-cells = <0>;