Lines Matching +full:0 +full:xfffffd40
46 reg = <0x20000000 0x08000000>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
65 reg = <0x00300000 0x14000>;
70 reg = <0x00500000 0x4000>;
91 reg = <0xfffff000 0x200>;
97 reg = <0xfffffc00 0x100>;
101 #size-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
118 plla: pllack@0 {
120 #clock-cells = <0>;
123 reg = <0>;
126 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
132 #clock-cells = <0>;
138 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
144 #clock-cells = <0>;
147 atmel,clk-output-range = <0 120000000>;
148 atmel,clk-divisors = <1 2 4 0>;
154 #clock-cells = <0>;
155 atmel,clk-divisors = <1 2 4 0>;
162 #size-cells = <0>;
166 prog0: prog@0 {
167 #clock-cells = <0>;
168 reg = <0>;
169 interrupts = <AT91_PMC_PCKRDY(0)>;
173 #clock-cells = <0>;
179 #clock-cells = <0>;
185 #clock-cells = <0>;
194 #size-cells = <0>;
197 #clock-cells = <0>;
203 #clock-cells = <0>;
209 #clock-cells = <0>;
215 #clock-cells = <0>;
221 #clock-cells = <0>;
227 #clock-cells = <0>;
236 #size-cells = <0>;
241 #clock-cells = <0>;
247 #clock-cells = <0>;
253 #clock-cells = <0>;
259 #clock-cells = <0>;
264 #clock-cells = <0>;
269 #clock-cells = <0>;
274 #clock-cells = <0>;
279 #clock-cells = <0>;
284 #clock-cells = <0>;
289 #clock-cells = <0>;
294 #clock-cells = <0>;
299 #clock-cells = <0>;
304 #clock-cells = <0>;
309 #clock-cells = <0>;
314 #clock-cells = <0>;
319 #clock-cells = <0>;
324 #clock-cells = <0>;
329 #clock-cells = <0>;
334 #clock-cells = <0>;
339 #clock-cells = <0>;
344 #clock-cells = <0>;
349 #clock-cells = <0>;
354 #clock-cells = <0>;
359 #clock-cells = <0>;
367 reg = <0xffffe200 0x200>;
372 reg = <0xffffe800 0x200>;
377 reg = <0xfffffd30 0xf>;
384 reg = <0xfff7c000 0x100>;
385 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
392 reg = <0xfffffd00 0x10>;
398 reg = <0xfffffd10 0x10>;
406 ranges = <0xfffff200 0xfffff200 0xa00>;
407 reg = <0xfffff200 0x200
408 0xfffff400 0x200
409 0xfffff600 0x200
410 0xfffff800 0x200
411 0xfffffa00 0x200
416 0xfffffffb 0xffffe07f /* pioA */
417 0x0007ffff 0x39072fff /* pioB */
418 0xffffffff 0x3ffffff8 /* pioC */
419 0xfffffbff 0xffffffff /* pioD */
420 0xffe00fff 0xfbfcff00 /* pioE */
425 pinctrl_dbgu: dbgu-0 {
433 pinctrl_usart0: usart0-0 {
439 pinctrl_usart0_rts: usart0_rts-0 {
444 pinctrl_usart0_cts: usart0_cts-0 {
451 pinctrl_usart1: usart1-0 {
453 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
457 pinctrl_usart1_rts: usart1_rts-0 {
462 pinctrl_usart1_cts: usart1_cts-0 {
469 pinctrl_usart2: usart2-0 {
475 pinctrl_usart2_rts: usart2_rts-0 {
480 pinctrl_usart2_cts: usart2_cts-0 {
487 pinctrl_nand: nand-0 {
495 pinctrl_macb_rmii: macb_rmii-0 {
509 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
523 pinctrl_mmc0_clk: mmc0_clk-0 {
528 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
531 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
534 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
541 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
547 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
556 pinctrl_mmc1_clk: mmc1_clk-0 {
561 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
567 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
574 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
580 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
589 pinctrl_ssc0_tx: ssc0_tx-0 {
591 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
596 pinctrl_ssc0_rx: ssc0_rx-0 {
605 pinctrl_ssc1_tx: ssc1_tx-0 {
612 pinctrl_ssc1_rx: ssc1_rx-0 {
621 pinctrl_spi0: spi0-0 {
623 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
630 pinctrl_spi1: spi1-0 {
639 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
643 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
647 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
651 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
655 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
659 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
663 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
667 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
671 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
677 pinctrl_fb: fb-0 {
713 pinctrl_ac97: ac97-0 {
715 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */
726 reg = <0xfffff200 0x200>;
738 reg = <0xfffff400 0x200>;
750 reg = <0xfffff600 0x200>;
762 reg = <0xfffff800 0x200>;
774 reg = <0xfffffa00 0x200>;
786 reg = <0xffffee00 0x200>;
789 pinctrl-0 = <&pinctrl_dbgu>;
797 reg = <0xfff8c000 0x200>;
802 pinctrl-0 = <&pinctrl_usart0>;
810 reg = <0xfff90000 0x200>;
815 pinctrl-0 = <&pinctrl_usart1>;
823 reg = <0xfff94000 0x200>;
828 pinctrl-0 = <&pinctrl_usart2>;
836 reg = <0xfff98000 0x4000>;
839 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
847 reg = <0xfff9c000 0x4000>;
850 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
858 reg = <0xfffa0000 0x4000>;
861 pinctrl-0 = <&pinctrl_ac97>;
869 reg = <0xfffbc000 0x100>;
872 pinctrl-0 = <&pinctrl_macb_rmii>;
880 reg = <0xfff78000 0x4000>;
889 reg = <0xfff88000 0x100>;
892 #size-cells = <0>;
899 reg = <0xfff80000 0x600>;
900 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
903 #size-cells = <0>;
911 reg = <0xfff84000 0x600>;
912 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
915 #size-cells = <0>;
923 reg = <0xfffffd40 0x10>;
934 #size-cells = <0>;
936 reg = <0xfffa4000 0x200>;
939 pinctrl-0 = <&pinctrl_spi0>;
947 #size-cells = <0>;
949 reg = <0xfffa8000 0x200>;
952 pinctrl-0 = <&pinctrl_spi1>;
960 reg = <0xfffb8000 0x300>;
970 reg = <0xfffac000 0x300>;
973 pinctrl-0 = <&pinctrl_can_rx_tx>;
980 reg = <0xfffffd20 0x10>;
988 reg = <0xfffffd50 0x10>;
996 reg = <0xfffffd60 0x50>;
1001 fb0: fb@0x00700000 {
1003 reg = <0x00700000 0x1000>;
1006 pinctrl-0 = <&pinctrl_fb>;
1016 reg = <0x40000000 0x10000000
1017 0xffffe000 0x200
1022 pinctrl-0 = <&pinctrl_nand>;
1025 0
1032 reg = <0x00a00000 0x100000>;
1040 i2c-gpio-0 {
1049 #size-cells = <0>;