Lines Matching +full:0 +full:xfffffd40
47 reg = <0x20000000 0x04000000>;
53 #clock-cells = <0>;
54 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
72 reg = <0x002ff000 0x2000>;
93 reg = <0xfffff000 0x200>;
99 reg = <0xffffea00 0x200>;
104 reg = <0xfffffc00 0x100>;
108 #size-cells = <0>;
114 #clock-cells = <0>;
121 #clock-cells = <0>;
127 #clock-cells = <0>;
134 #clock-cells = <0>;
138 plla: pllack@0 {
140 #clock-cells = <0>;
143 reg = <0>;
146 atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
152 #clock-cells = <0>;
163 #clock-cells = <0>;
166 atmel,clk-output-range = <0 105000000>;
167 atmel,clk-divisors = <1 2 4 0>;
173 #clock-cells = <0>;
174 atmel,clk-divisors = <1 2 4 0>;
181 #size-cells = <0>;
185 prog0: prog@0 {
186 #clock-cells = <0>;
187 reg = <0>;
188 interrupts = <AT91_PMC_PCKRDY(0)>;
192 #clock-cells = <0>;
201 #size-cells = <0>;
204 #clock-cells = <0>;
210 #clock-cells = <0>;
216 #clock-cells = <0>;
222 #clock-cells = <0>;
231 #size-cells = <0>;
236 #clock-cells = <0>;
242 #clock-cells = <0>;
248 #clock-cells = <0>;
254 #clock-cells = <0>;
259 #clock-cells = <0>;
264 #clock-cells = <0>;
269 #clock-cells = <0>;
274 #clock-cells = <0>;
279 #clock-cells = <0>;
285 #clock-cells = <0>;
289 #clock-cells = <0>;
294 #clock-cells = <0>;
299 #clock-cells = <0>;
304 #clock-cells = <0>;
309 #clock-cells = <0>;
314 #clock-cells = <0>;
319 #clock-cells = <0>;
324 #clock-cells = <0>;
329 #clock-cells = <0>;
334 #clock-cells = <0>;
339 #clock-cells = <0>;
344 #clock-cells = <0>;
349 #clock-cells = <0>;
354 #clock-cells = <0>;
359 #clock-cells = <0>;
367 reg = <0xfffffd00 0x10>;
373 reg = <0xfffffd10 0x10>;
379 reg = <0xfffffd30 0xf>;
386 reg = <0xfffa0000 0x100>;
387 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
388 18 IRQ_TYPE_LEVEL_HIGH 0
389 19 IRQ_TYPE_LEVEL_HIGH 0>;
396 reg = <0xfffdc000 0x100>;
397 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
398 27 IRQ_TYPE_LEVEL_HIGH 0
399 28 IRQ_TYPE_LEVEL_HIGH 0>;
406 reg = <0xfffff400 0x200>;
418 reg = <0xfffff600 0x200>;
430 reg = <0xfffff800 0x200>;
444 ranges = <0xfffff400 0xfffff400 0x600>;
445 reg = <0xfffff400 0x200 /* pioA */
446 0xfffff600 0x200 /* pioB */
447 0xfffff800 0x200 /* pioC */
452 0xffffffff 0xffc00c3b /* pioA */
453 0xffffffff 0x7fff3ccf /* pioB */
454 0xffffffff 0x007fffff /* pioC */
461 pinctrl_dbgu: dbgu-0 {
469 pinctrl_usart0: usart0-0 {
475 pinctrl_usart0_rts: usart0_rts-0 {
480 pinctrl_usart0_cts: usart0_cts-0 {
485 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
491 pinctrl_usart0_dcd: usart0_dcd-0 {
496 pinctrl_usart0_ri: usart0_ri-0 {
503 pinctrl_usart1: usart1-0 {
509 pinctrl_usart1_rts: usart1_rts-0 {
514 pinctrl_usart1_cts: usart1_cts-0 {
521 pinctrl_usart2: usart2-0 {
527 pinctrl_usart2_rts: usart2_rts-0 {
532 pinctrl_usart2_cts: usart2_cts-0 {
539 pinctrl_usart3: usart3-0 {
545 pinctrl_usart3_rts: usart3_rts-0 {
550 pinctrl_usart3_cts: usart3_cts-0 {
557 pinctrl_uart0: uart0-0 {
565 pinctrl_uart1: uart1-0 {
573 pinctrl_nand: nand-0 {
581 pinctrl_macb_rmii: macb_rmii-0 {
595 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
621 pinctrl_mmc0_clk: mmc0_clk-0 {
626 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
632 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
639 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
642 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */
645 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
654 pinctrl_ssc0_tx: ssc0_tx-0 {
661 pinctrl_ssc0_rx: ssc0_rx-0 {
670 pinctrl_spi0: spi0-0 {
672 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
679 pinctrl_spi1: spi1-0 {
681 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */
688 pinctrl_i2c_gpio0: i2c_gpio0-0 {
696 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
700 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
704 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
708 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
712 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
716 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
720 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
724 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
728 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
734 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
738 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
742 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
746 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
747 atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
750 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
754 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
758 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
762 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
766 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
774 reg = <0xfffff200 0x200>;
777 pinctrl-0 = <&pinctrl_dbgu>;
785 reg = <0xfffb0000 0x200>;
790 pinctrl-0 = <&pinctrl_usart0>;
798 reg = <0xfffb4000 0x200>;
803 pinctrl-0 = <&pinctrl_usart1>;
811 reg = <0xfffb8000 0x200>;
816 pinctrl-0 = <&pinctrl_usart2>;
824 reg = <0xfffd0000 0x200>;
829 pinctrl-0 = <&pinctrl_usart3>;
837 reg = <0xfffd4000 0x200>;
842 pinctrl-0 = <&pinctrl_uart0>;
850 reg = <0xfffd8000 0x200>;
855 pinctrl-0 = <&pinctrl_uart1>;
863 reg = <0xfffc4000 0x100>;
866 pinctrl-0 = <&pinctrl_macb_rmii>;
874 reg = <0xfffa4000 0x4000>;
883 reg = <0xfffac000 0x100>;
886 #size-cells = <0>;
893 reg = <0xfffa8000 0x600>;
894 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
896 #size-cells = <0>;
905 reg = <0xfffbc000 0x4000>;
908 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
916 #size-cells = <0>;
918 reg = <0xfffc8000 0x200>;
921 pinctrl-0 = <&pinctrl_spi0>;
929 #size-cells = <0>;
931 reg = <0xfffcc000 0x200>;
934 pinctrl-0 = <&pinctrl_spi1>;
942 #size-cells = <0>;
944 reg = <0xfffe0000 0x100>;
945 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
949 atmel,adc-channels-used = <0xf>;
956 trigger@0 {
957 reg = <0>;
958 trigger-name = "timer-counter-0";
959 trigger-value = <0x1>;
964 trigger-value = <0x3>;
970 trigger-value = <0x5>;
976 trigger-value = <0xd>;
983 reg = <0xfffffd20 0x10>;
991 reg = <0xfffffd40 0x10>;
1002 reg = <0xfffffd50 0x10>;
1011 reg = <0x40000000 0x10000000
1012 0xffffe800 0x200
1017 pinctrl-0 = <&pinctrl_nand>;
1020 0
1027 reg = <0x00500000 0x100000>;
1035 i2c@0 {
1044 #size-cells = <0>;
1046 pinctrl-0 = <&pinctrl_i2c_gpio0>;