Lines Matching +full:0 +full:xd0000000
12 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
13 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
17 * registers mapped at 0xd0000000. If you have such a device you will
22 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
47 reg = <0 0x00000000 0 0x40000000>; /* 1GB */
51 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
52 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
61 pcie@1,0 {
62 /* Port 0, Lane 0 */
70 pcie@5,0 {
71 /* Port 1, Lane 0 */
87 spi-flash@0 {
92 reg = <0>; /* Chip select 0 */
111 reg = <0x00000000 0x000d0000>; /* 832KB */
116 reg = <0x000d0000 0x002d0000>; /* 2880KB */
121 reg = <0x003a0000 0x00430000>; /* 4250KB */
126 reg = <0x007d0000 0x00010000>; /* 64KB */
131 reg = <0x007e0000 0x00010000>; /* 64KB */
136 reg = <0x007f0000 0x00010000>; /* 64KB */
147 reg = <0x30>;
159 * pin being sampled at reset (bit 0 of SAR).
173 reg = <0x12100 0x100>;
174 clocks = <&coreclk 0>;
183 phy0: ethernet-phy@0 { /* Marvell 88E1512 */
184 reg = <0>;
194 pinctrl-0 = <&ge0_rgmii_pins>;
201 pinctrl-0 = <&ge1_rgmii_pins>;
213 #size-cells = <0>;
214 pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin