arm/dts/armada-xp-mv78460.dtsi

6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8  * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
64 		#address-cells = <1>;
65 		#size-cells = <0>;
66 		enable-method = "marvell,armada-xp-smp";
70 			compatible = "marvell,sheeva-v7";
73 			clock-latency = <1000000>;
78 			compatible = "marvell,sheeva-v7";
81 			clock-latency = <1000000>;
86 			compatible = "marvell,sheeva-v7";
89 			clock-latency = <1000000>;
94 			compatible = "marvell,sheeva-v7";
97 			clock-latency = <1000000>;
108 			compatible = "marvell,armada-xp-pcie";
112 			#address-cells = <3>;
113 			#size-cells = <2>;
115 			msi-parent = <&mpic>;
116 			bus-range = <0x00 0xff>;
155 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
157 				#address-cells = <3>;
158 				#size-cells = <2>;
159 				#interrupt-cells = <1>;
162 				bus-range = <0x00 0xff>;
163 				interrupt-map-mask = <0 0 0 0>;
164 				interrupt-map = <0 0 0 0 &mpic 58>;
165 				marvell,pcie-port = <0>;
166 				marvell,pcie-lane = <0>;
173 				assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
175 				#address-cells = <3>;
176 				#size-cells = <2>;
177 				#interrupt-cells = <1>;
180 				bus-range = <0x00 0xff>;
181 				interrupt-map-mask = <0 0 0 0>;
182 				interrupt-map = <0 0 0 0 &mpic 59>;
183 				marvell,pcie-port = <0>;
184 				marvell,pcie-lane = <1>;
191 				assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
193 				#address-cells = <3>;
194 				#size-cells = <2>;
195 				#interrupt-cells = <1>;
198 				bus-range = <0x00 0xff>;
199 				interrupt-map-mask = <0 0 0 0>;
200 				interrupt-map = <0 0 0 0 &mpic 60>;
201 				marvell,pcie-port = <0>;
202 				marvell,pcie-lane = <2>;
209 				assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
211 				#address-cells = <3>;
212 				#size-cells = <2>;
213 				#interrupt-cells = <1>;
216 				bus-range = <0x00 0xff>;
217 				interrupt-map-mask = <0 0 0 0>;
218 				interrupt-map = <0 0 0 0 &mpic 61>;
219 				marvell,pcie-port = <0>;
220 				marvell,pcie-lane = <3>;
227 				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
229 				#address-cells = <3>;
230 				#size-cells = <2>;
231 				#interrupt-cells = <1>;
234 				bus-range = <0x00 0xff>;
235 				interrupt-map-mask = <0 0 0 0>;
236 				interrupt-map = <0 0 0 0 &mpic 62>;
237 				marvell,pcie-port = <1>;
238 				marvell,pcie-lane = <0>;
245 				assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
247 				#address-cells = <3>;
248 				#size-cells = <2>;
249 				#interrupt-cells = <1>;
252 				bus-range = <0x00 0xff>;
253 				interrupt-map-mask = <0 0 0 0>;
254 				interrupt-map = <0 0 0 0 &mpic 63>;
255 				marvell,pcie-port = <1>;
256 				marvell,pcie-lane = <1>;
263 				assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
265 				#address-cells = <3>;
266 				#size-cells = <2>;
267 				#interrupt-cells = <1>;
270 				bus-range = <0x00 0xff>;
271 				interrupt-map-mask = <0 0 0 0>;
272 				interrupt-map = <0 0 0 0 &mpic 64>;
273 				marvell,pcie-port = <1>;
274 				marvell,pcie-lane = <2>;
281 				assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
283 				#address-cells = <3>;
284 				#size-cells = <2>;
285 				#interrupt-cells = <1>;
288 				bus-range = <0x00 0xff>;
289 				interrupt-map-mask = <0 0 0 0>;
290 				interrupt-map = <0 0 0 0 &mpic 65>;
291 				marvell,pcie-port = <1>;
292 				marvell,pcie-lane = <3>;
299 				assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
301 				#address-cells = <3>;
302 				#size-cells = <2>;
303 				#interrupt-cells = <1>;
306 				bus-range = <0x00 0xff>;
307 				interrupt-map-mask = <0 0 0 0>;
308 				interrupt-map = <0 0 0 0 &mpic 99>;
309 				marvell,pcie-port = <2>;
310 				marvell,pcie-lane = <0>;
317 				assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
319 				#address-cells = <3>;
320 				#size-cells = <2>;
321 				#interrupt-cells = <1>;
324 				bus-range = <0x00 0xff>;
325 				interrupt-map-mask = <0 0 0 0>;
326 				interrupt-map = <0 0 0 0 &mpic 103>;
327 				marvell,pcie-port = <3>;
328 				marvell,pcie-lane = <0>;
334 		internal-regs {
335 			gpio0: gpio@18100 {
336 				compatible = "marvell,orion-gpio";
339 				gpio-controller;
340 				#gpio-cells = <2>;
341 				interrupt-controller;
342 				#interrupt-cells = <2>;
346 			gpio1: gpio@18140 {
347 				compatible = "marvell,orion-gpio";
350 				gpio-controller;
351 				#gpio-cells = <2>;
352 				interrupt-controller;
353 				#interrupt-cells = <2>;
357 			gpio2: gpio@18180 {
358 				compatible = "marvell,orion-gpio";
361 				gpio-controller;
362 				#gpio-cells = <2>;
363 				interrupt-controller;
364 				#interrupt-cells = <2>;
369 				compatible = "marvell,armada-xp-neta";
380 	compatible = "marvell,mv78460-pinctrl";