arm/dts/armada-xp-mv78260.dtsi

6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8  * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
63 		#address-cells = <1>;
64 		#size-cells = <0>;
65 		enable-method = "marvell,armada-xp-smp";
69 			compatible = "marvell,sheeva-v7";
72 			clock-latency = <1000000>;
77 			compatible = "marvell,sheeva-v7";
80 			clock-latency = <1000000>;
86 		 * MV78260 has 3 PCIe units Gen2.0: Two units can be
87 		 * configured as x4 or quad x1 lanes. One unit is
88 		 * x4 only.
90 		pciec: pcie@82000000 {
91 			compatible = "marvell,armada-xp-pcie";
95 			#address-cells = <3>;
96 			#size-cells = <2>;
98 			msi-parent = <&mpic>;
99 			bus-range = <0x00 0xff>;
117 				0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
118 				0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
132 			pcie1: pcie@1,0 {
134 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
136 				#address-cells = <3>;
137 				#size-cells = <2>;
138 				#interrupt-cells = <1>;
141 				bus-range = <0x00 0xff>;
142 				interrupt-map-mask = <0 0 0 0>;
143 				interrupt-map = <0 0 0 0 &mpic 58>;
144 				marvell,pcie-port = <0>;
145 				marvell,pcie-lane = <0>;
150 			pcie2: pcie@2,0 {
152 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
154 				#address-cells = <3>;
155 				#size-cells = <2>;
156 				#interrupt-cells = <1>;
159 				bus-range = <0x00 0xff>;
160 				interrupt-map-mask = <0 0 0 0>;
161 				interrupt-map = <0 0 0 0 &mpic 59>;
162 				marvell,pcie-port = <0>;
163 				marvell,pcie-lane = <1>;
168 			pcie3: pcie@3,0 {
170 				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
172 				#address-cells = <3>;
173 				#size-cells = <2>;
174 				#interrupt-cells = <1>;
177 				bus-range = <0x00 0xff>;
178 				interrupt-map-mask = <0 0 0 0>;
179 				interrupt-map = <0 0 0 0 &mpic 60>;
180 				marvell,pcie-port = <0>;
181 				marvell,pcie-lane = <2>;
186 			pcie4: pcie@4,0 {
188 				assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
190 				#address-cells = <3>;
191 				#size-cells = <2>;
192 				#interrupt-cells = <1>;
193 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
194 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
195 				bus-range = <0x00 0xff>;
196 				interrupt-map-mask = <0 0 0 0>;
197 				interrupt-map = <0 0 0 0 &mpic 61>;
198 				marvell,pcie-port = <0>;
199 				marvell,pcie-lane = <3>;
204 			pcie5: pcie@5,0 {
206 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
208 				#address-cells = <3>;
209 				#size-cells = <2>;
210 				#interrupt-cells = <1>;
213 				bus-range = <0x00 0xff>;
214 				interrupt-map-mask = <0 0 0 0>;
215 				interrupt-map = <0 0 0 0 &mpic 62>;
216 				marvell,pcie-port = <1>;
217 				marvell,pcie-lane = <0>;
222 			pcie6: pcie@6,0 {
224 				assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
226 				#address-cells = <3>;
227 				#size-cells = <2>;
228 				#interrupt-cells = <1>;
231 				bus-range = <0x00 0xff>;
232 				interrupt-map-mask = <0 0 0 0>;
233 				interrupt-map = <0 0 0 0 &mpic 63>;
234 				marvell,pcie-port = <1>;
235 				marvell,pcie-lane = <1>;
240 			pcie7: pcie@7,0 {
242 				assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
244 				#address-cells = <3>;
245 				#size-cells = <2>;
246 				#interrupt-cells = <1>;
249 				bus-range = <0x00 0xff>;
250 				interrupt-map-mask = <0 0 0 0>;
251 				interrupt-map = <0 0 0 0 &mpic 64>;
252 				marvell,pcie-port = <1>;
253 				marvell,pcie-lane = <2>;
258 			pcie8: pcie@8,0 {
260 				assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
262 				#address-cells = <3>;
263 				#size-cells = <2>;
264 				#interrupt-cells = <1>;
267 				bus-range = <0x00 0xff>;
268 				interrupt-map-mask = <0 0 0 0>;
269 				interrupt-map = <0 0 0 0 &mpic 65>;
270 				marvell,pcie-port = <1>;
271 				marvell,pcie-lane = <3>;
276 			pcie9: pcie@9,0 {
278 				assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
280 				#address-cells = <3>;
281 				#size-cells = <2>;
282 				#interrupt-cells = <1>;
285 				bus-range = <0x00 0xff>;
286 				interrupt-map-mask = <0 0 0 0>;
287 				interrupt-map = <0 0 0 0 &mpic 99>;
288 				marvell,pcie-port = <2>;
289 				marvell,pcie-lane = <0>;
295 		internal-regs {
297 				compatible = "marvell,orion-gpio";
300 				gpio-controller;
301 				#gpio-cells = <2>;
302 				interrupt-controller;
303 				#interrupt-cells = <2>;
308 				compatible = "marvell,orion-gpio";
311 				gpio-controller;
312 				#gpio-cells = <2>;
313 				interrupt-controller;
314 				#interrupt-cells = <2>;
319 				compatible = "marvell,orion-gpio";
322 				gpio-controller;
323 				#gpio-cells = <2>;
324 				interrupt-controller;
325 				#interrupt-cells = <2>;
330 				compatible = "marvell,armada-xp-neta";
341 	compatible = "marvell,mv78260-pinctrl";