Lines Matching +full:0 +full:x00002000
64 #size-cells = <0>;
67 cpu@0 {
70 reg = <0>;
71 clocks = <&cpuclk 0>;
86 * MV78260 has 3 PCIe units Gen2.0: Two units can be
99 bus-range = <0x00 0xff>;
102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
106 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
107 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
108 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
109 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
110 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
111 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
112 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
113 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
114 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
115 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
116 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
117 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
118 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
120 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
121 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
122 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
123 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
124 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
125 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
126 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
127 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
129 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
130 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
132 pcie1: pcie@1,0 {
134 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
135 reg = <0x0800 0 0 0 0>;
139 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
140 0x81000000 0 0 0x81000000 0x1 0 1 0>;
141 bus-range = <0x00 0xff>;
142 interrupt-map-mask = <0 0 0 0>;
143 interrupt-map = <0 0 0 0 &mpic 58>;
144 marvell,pcie-port = <0>;
145 marvell,pcie-lane = <0>;
150 pcie2: pcie@2,0 {
152 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
153 reg = <0x1000 0 0 0 0>;
157 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
158 0x81000000 0 0 0x81000000 0x2 0 1 0>;
159 bus-range = <0x00 0xff>;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 59>;
162 marvell,pcie-port = <0>;
168 pcie3: pcie@3,0 {
170 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
171 reg = <0x1800 0 0 0 0>;
175 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
176 0x81000000 0 0 0x81000000 0x3 0 1 0>;
177 bus-range = <0x00 0xff>;
178 interrupt-map-mask = <0 0 0 0>;
179 interrupt-map = <0 0 0 0 &mpic 60>;
180 marvell,pcie-port = <0>;
186 pcie4: pcie@4,0 {
188 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
189 reg = <0x2000 0 0 0 0>;
193 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
194 0x81000000 0 0 0x81000000 0x4 0 1 0>;
195 bus-range = <0x00 0xff>;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 61>;
198 marvell,pcie-port = <0>;
204 pcie5: pcie@5,0 {
206 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
207 reg = <0x2800 0 0 0 0>;
211 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
212 0x81000000 0 0 0x81000000 0x5 0 1 0>;
213 bus-range = <0x00 0xff>;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-lane = <0>;
222 pcie6: pcie@6,0 {
224 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
225 reg = <0x3000 0 0 0 0>;
229 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
230 0x81000000 0 0 0x81000000 0x6 0 1 0>;
231 bus-range = <0x00 0xff>;
232 interrupt-map-mask = <0 0 0 0>;
233 interrupt-map = <0 0 0 0 &mpic 63>;
240 pcie7: pcie@7,0 {
242 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
243 reg = <0x3800 0 0 0 0>;
247 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
248 0x81000000 0 0 0x81000000 0x7 0 1 0>;
249 bus-range = <0x00 0xff>;
250 interrupt-map-mask = <0 0 0 0>;
251 interrupt-map = <0 0 0 0 &mpic 64>;
258 pcie8: pcie@8,0 {
260 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
261 reg = <0x4000 0 0 0 0>;
265 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
266 0x81000000 0 0 0x81000000 0x8 0 1 0>;
267 bus-range = <0x00 0xff>;
268 interrupt-map-mask = <0 0 0 0>;
269 interrupt-map = <0 0 0 0 &mpic 65>;
276 pcie9: pcie@9,0 {
278 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
279 reg = <0x4800 0 0 0 0>;
283 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
284 0x81000000 0 0 0x81000000 0x9 0 1 0>;
285 bus-range = <0x00 0xff>;
286 interrupt-map-mask = <0 0 0 0>;
287 interrupt-map = <0 0 0 0 &mpic 99>;
289 marvell,pcie-lane = <0>;
298 reg = <0x18100 0x40>;
309 reg = <0x18140 0x40>;
320 reg = <0x18180 0x40>;
331 reg = <0x34000 0x4000>;