Lines Matching +full:armadaxp +full:- +full:gpio

3  * (DB-MV784MP-GP)
5 * Copyright (C) 2013-2014 Marvell
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is dual-licensed: you can use it either under the terms
52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
59 /dts-v1/;
60 #include <dt-bindings/gpio/gpio.h>
61 #include "armada-xp-mv78460.dtsi"
64 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
65 …compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370
68 stdout-path = "serial0:115200n8";
78 * 8 GB of plug-in RAM modules by default.The amount
92 ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
103 devbus-bootcs {
109 devbus,bus-width = <16>;
110 devbus,turn-off-ps = <60000>;
111 devbus,badr-skew-ps = <0>;
112 devbus,acc-first-ps = <124000>;
113 devbus,acc-next-ps = <248000>;
114 devbus,rd-setup-ps = <0>;
115 devbus,rd-hold-ps = <0>;
118 devbus,sync-enable = <0>;
119 devbus,wr-high-ps = <60000>;
120 devbus,wr-low-ps = <60000>;
121 devbus,ale-wr-ps = <60000>;
125 compatible = "cfi-flash";
127 bank-width = <2>;
131 pcie-controller {
152 internal-regs {
155 u-boot,dm-pre-reloc;
167 pinctrl-0 = <&pic_pins>;
168 pinctrl-names = "default";
169 pic_pins: pic-pins-0 {
172 marvell,function = "gpio";
176 nr-ports = <2>;
181 phy0: ethernet-phy@0 {
185 phy1: ethernet-phy@1 {
189 phy2: ethernet-phy@2 {
193 phy3: ethernet-phy@3 {
201 phy-mode = "qsgmii";
206 phy-mode = "qsgmii";
211 phy-mode = "qsgmii";
216 phy-mode = "qsgmii";
219 /* Front-side USB slot */
224 /* Back-side USB slot */
231 u-boot,dm-pre-reloc;
233 spi-flash@0 {
234 u-boot,dm-pre-reloc;
235 #address-cells = <1>;
236 #size-cells = <1>;
237 compatible = "n25q128a13", "jedec,spi-nor";
239 spi-max-frequency = <108000000>;
245 num-cs = <1>;
246 marvell,nand-keep-config;
247 marvell,nand-enable-arbiter;
248 nand-on-flash-bbt;