arm/dts/armada-cp110-slave.dtsi

4  * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 	cp110-slave {
51 		#address-cells = <2>;
52 		#size-cells = <2>;
53 		compatible = "simple-bus";
54 		interrupt-parent = <&gic>;
57 		config-space {
58 			#address-cells = <1>;
59 			#size-cells = <1>;
60 			compatible = "simple-bus";
61 			interrupt-parent = <&gic>;
65 				compatible = "marvell,armada-7k-pp22";
68 				clock-names = "pp_clk", "gop_clk", "mg_clk";
70 				dma-coherent;
74 					port-id = <0>;
75 					gop-port-id = <0>;
81 					port-id = <1>;
82 					gop-port-id = <2>;
88 					port-id = <2>;
89 					gop-port-id = <3>;
95 				#address-cells = <1>;
96 				#size-cells = <0>;
97 				compatible = "marvell,orion-mdio";
101 			cps_syscon0: system-controller@440000 {
102 				compatible = "marvell,cp110-system-controller0",
105 				#clock-cells = <2>;
106 				core-clock-output-names =
107 					"cps-apll", "cps-ppv2-core", "cps-eip",
108 					"cps-core", "cps-nand-core";
109 				gate-clock-output-names =
110 					"cps-audio", "cps-communit", "cps-nand",
111 					"cps-ppv2", "cps-sdio", "cps-mg-domain",
112 					"cps-mg-core", "cps-xor1", "cps-xor0",
113 					"cps-gop-dp", "none", "cps-pcie_x10",
114 					"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
115 					"cps-sata", "cps-sata-usb", "cps-main",
116 					"cps-sd-mmc", "none", "none",
117 					"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
118 					"cps-usb3dev", "cps-eip150", "cps-eip197";
121 			cps_pinctl: cps-pinctl@440000 {
122 				compatible = "marvell,mvebu-pinctrl",
123 					     "marvell,armada-8k-cps-pinctrl";
124 				bank-name ="cp1-110";
126 				pin-count = <63>;
127 				max-func = <0xf>;
129 				cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
134 				cps_spi1_pins: cps-spi-pins-1 {
141 				compatible = "marvell,orion-gpio";
145 				gpio-controller;
146 				#gpio-cells = <2>;
150 				compatible = "marvell,orion-gpio";
154 				gpio-controller;
155 				#gpio-cells = <2>;
159 				compatible = "marvell,armada-8k-ahci";
167 				compatible = "marvell,armada-8k-xhci",
168 					     "generic-xhci";
170 				dma-coherent;
177 				compatible = "marvell,armada-8k-xhci",
178 					     "generic-xhci";
180 				dma-coherent;
187 				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
190 				dma-coherent;
191 				msi-parent = <&gic_v2m0>;
196 				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
199 				dma-coherent;
200 				msi-parent = <&gic_v2m0>;
205 				compatible = "marvell,armada-380-spi";
207 				#address-cells = <0x1>;
208 				#size-cells = <0x0>;
209 				cell-index = <1>;
215 				compatible = "marvell,armada-380-spi";
217 				#address-cells = <1>;
218 				#size-cells = <0>;
219 				cell-index = <2>;
225 				compatible = "marvell,mv78230-i2c";
227 				#address-cells = <1>;
228 				#size-cells = <0>;
235 				compatible = "marvell,mv78230-i2c";
237 				#address-cells = <1>;
238 				#size-cells = <0>;
245 				compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
248 				mux-bitcount = <4>;
249 				max-lanes = <6>;
253 				compatible = "marvell,mvebu-utmi-2.6.0";
254 				reg = <0x580000 0x1000>,	/* utmi-unit */
255 				      <0x440420 0x4>,		/* usb-cfg */
256 				      <0x440440 0x4>;		/* utmi-cfg */
257 				utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
263 			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
266 			reg-names = "ctrl", "config";
267 			#address-cells = <3>;
268 			#size-cells = <2>;
269 			#interrupt-cells = <1>;
271 			dma-coherent;
272 			msi-parent = <&gic_v2m0>;
274 			bus-range = <0 0xff>;
278 				/* non-prefetchable memory */
280 			interrupt-map-mask = <0 0 0 0>;
281 			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
283 			num-lanes = <1>;
289 			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
292 			reg-names = "ctrl", "config";
293 			#address-cells = <3>;
294 			#size-cells = <2>;
295 			#interrupt-cells = <1>;
297 			dma-coherent;
298 			msi-parent = <&gic_v2m0>;
300 			bus-range = <0 0xff>;
304 				/* non-prefetchable memory */
306 			interrupt-map-mask = <0 0 0 0>;
307 			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
310 			num-lanes = <1>;
316 			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
319 			reg-names = "ctrl", "config";
320 			#address-cells = <3>;
321 			#size-cells = <2>;
322 			#interrupt-cells = <1>;
324 			dma-coherent;
325 			msi-parent = <&gic_v2m0>;
327 			bus-range = <0 0xff>;
331 				/* non-prefetchable memory */
333 			interrupt-map-mask = <0 0 0 0>;
334 			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
337 			num-lanes = <1>;