Lines Matching +full:0 +full:xff
28 reg = <0x0 0x0 0x0 0x80000000>;
34 #size-cells = <0>;
39 pinctrl-0 = <&cpm_xhci_vbus_pins>;
60 * eMMC [0-10]
63 /* 0 1 2 3 4 5 6 7 8 9 */
65 1 3 0 0 0 0 0 0 0 3 >;
71 pinctrl-0 = <&ap_emmc_pins>;
79 * [0-31] = 0xff: Keep default CP0_shared_pins:
93 * [50] 10G port 0 interrupt
102 /* 0 1 2 3 4 5 6 7 8 9 */
103 pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
104 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
105 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
106 0xff 0 7 0xa 7 2 2 2 2 0xa
107 7 7 8 8 0 0 0 0 0 0
108 0 0 0 0 0 0 0xe 0xe 0xe 0xe
109 0xe 0xe 0 >;
113 marvell,function = <0>;
118 marvell,function = <0>;
125 pinctrl-0 = <&cpm_sdhci_pins>;
134 pinctrl-0 = <&cpm_pcie_reset_pins>;
141 pinctrl-0 = <&cpm_i2c0_pins>;
148 pinctrl-0 = <&cpm_i2c1_pins>;
158 ge_phy: ethernet-phy@0 {
159 reg = <0>;
166 * Lane 0: PCIe0 (x4)
219 * [0-5] TDM
220 * [6,7] CP1_UART 0
236 * [31] 10G Port 0 phy reset
237 * [32-62] = 0xff: Keep default CP1_shared_pins:
239 /* 0 1 2 3 4 5 6 7 8 9 */
240 pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0
241 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
242 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0
243 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
244 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
245 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
246 0xff 0xff 0xff>;
251 pinctrl-0 = <&cps_spi1_pins>;
254 spi-flash@0 {
258 reg = <0>;
266 partition@0 {
268 reg = <0 0x200000>;
272 reg = <0x200000 0xce0000>;
281 * Lane 0: SGMII1
282 * Lane 1: SATA 0
283 * Lane 2: USB HOST 0