Lines Matching +full:armada +full:- +full:370 +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
19 model = "Marvell Armada 38x family SoC";
30 compatible = "arm,cortex-a9-pmu";
31 interrupts-extended = <&mpic 3>;
35 compatible = "marvell,armada380-mbus", "simple-bus";
36 u-boot,dm-pre-reloc;
37 #address-cells = <2>;
38 #size-cells = <1>;
40 interrupt-parent = <&gic>;
41 pcie-mem-aperture = <0xe0000000 0x8000000>;
42 pcie-io-aperture = <0xe8000000 0x100000>;
49 devbus_bootcs: devbus-bootcs {
50 compatible = "marvell,mvebu-devbus";
53 #address-cells = <1>;
54 #size-cells = <1>;
59 devbus_cs0: devbus-cs0 {
60 compatible = "marvell,mvebu-devbus";
63 #address-cells = <1>;
64 #size-cells = <1>;
69 devbus_cs1: devbus-cs1 {
70 compatible = "marvell,mvebu-devbus";
73 #address-cells = <1>;
74 #size-cells = <1>;
79 devbus_cs2: devbus-cs2 {
80 compatible = "marvell,mvebu-devbus";
83 #address-cells = <1>;
84 #size-cells = <1>;
89 devbus_cs3: devbus-cs3 {
90 compatible = "marvell,mvebu-devbus";
93 #address-cells = <1>;
94 #size-cells = <1>;
99 internal-regs {
100 compatible = "simple-bus";
101 u-boot,dm-pre-reloc;
102 #address-cells = <1>;
103 #size-cells = <1>;
106 L2: cache-controller@8000 {
107 compatible = "arm,pl310-cache";
109 cache-unified;
110 cache-level = <2>;
111 arm,double-linefill-incr = <0>;
112 arm,double-linefill-wrap = <0>;
113 arm,double-linefill = <0>;
114 prefetch-data = <1>;
118 compatible = "arm,cortex-a9-scu";
123 compatible = "arm,cortex-a9-global-timer";
130 compatible = "arm,cortex-a9-twd-timer";
136 gic: interrupt-controller@d000 {
137 compatible = "arm,cortex-a9-gic";
138 #interrupt-cells = <3>;
139 #size-cells = <0>;
140 interrupt-controller;
146 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
148 #address-cells = <1>;
149 #size-cells = <0>;
151 timeout-ms = <1000>;
157 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
159 #address-cells = <1>;
160 #size-cells = <0>;
162 timeout-ms = <1000>;
168 compatible = "snps,dw-apb-uart";
170 reg-shift = <2>;
172 reg-io-width = <1>;
178 compatible = "snps,dw-apb-uart";
180 reg-shift = <2>;
182 reg-io-width = <1>;
190 ge0_rgmii_pins: ge-rgmii-pins-0 {
198 ge1_rgmii_pins: ge-rgmii-pins-1 {
206 i2c0_pins: i2c-pins-0 {
211 mdio_pins: mdio-pins {
216 ref_clk0_pins: ref-clk-pins-0 {
221 ref_clk1_pins: ref-clk-pins-1 {
226 spi0_pins: spi-pins-0 {
232 spi1_pins: spi-pins-1 {
238 nand_pins: nand-pins {
247 nand_rb: nand-rb {
252 uart0_pins: uart-pins-0 {
257 uart1_pins: uart-pins-1 {
262 sdhci_pins: sdhci-pins {
270 sata0_pins: sata-pins-0 {
275 sata1_pins: sata-pins-1 {
280 sata2_pins: sata-pins-2 {
285 sata3_pins: sata-pins-3 {
291 gpio0: gpio@18100 {
292 compatible = "marvell,armada-370-gpio",
293 "marvell,orion-gpio";
295 reg-names = "gpio", "pwm";
297 gpio-controller;
298 #gpio-cells = <2>;
299 #pwm-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
309 gpio1: gpio@18140 {
310 compatible = "marvell,armada-370-gpio",
311 "marvell,orion-gpio";
313 reg-names = "gpio", "pwm";
315 gpio-controller;
316 #gpio-cells = <2>;
317 #pwm-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
327 systemc: system-controller@18200 {
328 compatible = "marvell,armada-380-system-controller",
329 "marvell,armada-370-xp-system-controller";
333 gateclk: clock-gating-control@18220 {
334 compatible = "marvell,armada-380-gating-clock";
337 #clock-cells = <1>;
340 coreclk: mvebu-sar@18600 {
341 compatible = "marvell,armada-380-core-clock";
343 #clock-cells = <1>;
346 mbusc: mbus-controller@20000 {
347 compatible = "marvell,mbus-controller";
352 mpic: interrupt-controller@20a00 {
355 #interrupt-cells = <1>;
356 #size-cells = <1>;
357 interrupt-controller;
358 msi-controller;
363 compatible = "marvell,armada-380-timer",
364 "marvell,armada-xp-timer";
366 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
373 clock-names = "nbclk", "fixed";
377 compatible = "marvell,armada-380-wdt";
380 clock-names = "nbclk", "fixed";
384 compatible = "marvell,armada-370-cpu-reset";
388 mpcore-soc-ctrl@20d20 {
389 compatible = "marvell,armada-380-mpcore-soc-ctrl";
393 coherencyfab: coherency-fabric@21010 {
394 compatible = "marvell,armada-380-coherency-fabric";
399 compatible = "marvell,armada-380-pmsu";
411 * from the one used in U-Boot and the
416 compatible = "marvell,armada-370-neta";
418 interrupts-extended = <&mpic 8>;
420 tx-csum-limit = <9800>;
425 compatible = "marvell,armada-370-neta";
427 interrupts-extended = <&mpic 10>;
433 compatible = "marvell,armada-370-neta";
435 interrupts-extended = <&mpic 12>;
441 compatible = "marvell,orion-ehci";
449 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
469 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
489 #address-cells = <1>;
490 #size-cells = <0>;
491 compatible = "marvell,orion-mdio";
497 compatible = "marvell,armada-38x-crypto";
499 reg-names = "regs";
504 clock-names = "cesa0", "cesa1",
506 marvell,crypto-srams = <&crypto_sram0>,
508 marvell,crypto-sram-size = <0x800>;
512 compatible = "marvell,armada-380-rtc";
514 reg-names = "rtc", "rtc-soc";
519 compatible = "marvell,armada-380-ahci";
527 compatible = "marvell,armada-380-neta-bm";
530 internal-mem = <&bm_bppi>;
535 compatible = "marvell,armada-380-ahci";
543 compatible = "marvell,armada-380-corediv-clock";
545 #clock-cells = <1>;
547 clock-output-names = "nand";
551 compatible = "marvell,armada380-thermal";
556 nand_controller: nand-controller@d0000 {
557 compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
559 #address-cells = <1>;
560 #size-cells = <0>;
567 compatible = "marvell,armada-380-sdhci";
568 reg-names = "sdhci", "mbus", "conf-sdio3";
574 mrvl,clk-delay-cycles = <0x1F>;
579 compatible = "marvell,armada-380-xhci";
587 compatible = "marvell,armada-380-xhci";
595 crypto_sram0: sa-sram0 {
596 compatible = "mmio-sram";
599 #address-cells = <1>;
600 #size-cells = <1>;
604 crypto_sram1: sa-sram1 {
605 compatible = "mmio-sram";
608 #address-cells = <1>;
609 #size-cells = <1>;
613 bm_bppi: bm-bppi {
614 compatible = "mmio-sram";
617 #address-cells = <1>;
618 #size-cells = <1>;
620 no-memory-wc;
625 compatible = "marvell,armada-380-spi",
626 "marvell,orion-spi";
628 #address-cells = <1>;
629 #size-cells = <0>;
630 cell-index = <0>;
637 compatible = "marvell,armada-380-spi",
638 "marvell,orion-spi";
640 #address-cells = <1>;
641 #size-cells = <0>;
642 cell-index = <1>;
652 compatible = "fixed-clock";
653 #clock-cells = <0>;
654 clock-frequency = <1000000000>;
659 compatible = "fixed-clock";
660 #clock-cells = <0>;
661 clock-frequency = <25000000>;