Lines Matching +full:orion +full:- +full:sdio
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/phy/phy.h>
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <1000000000>;
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <25000000>;
83 #address-cells = <1>;
84 #size-cells = <0>;
85 enable-method = "marvell,armada-375-smp";
89 compatible = "arm,cortex-a9";
94 compatible = "arm,cortex-a9";
100 compatible = "arm,cortex-a9-pmu";
101 interrupts-extended = <&mpic 3>;
105 compatible = "marvell,armada375-mbus", "simple-bus";
106 u-boot,dm-pre-reloc;
107 #address-cells = <2>;
108 #size-cells = <1>;
110 interrupt-parent = <&gic>;
111 pcie-mem-aperture = <0xe0000000 0x8000000>;
112 pcie-io-aperture = <0xe8000000 0x100000>;
119 devbus-bootcs {
120 compatible = "marvell,mvebu-devbus";
123 #address-cells = <1>;
124 #size-cells = <1>;
129 devbus-cs0 {
130 compatible = "marvell,mvebu-devbus";
133 #address-cells = <1>;
134 #size-cells = <1>;
139 devbus-cs1 {
140 compatible = "marvell,mvebu-devbus";
143 #address-cells = <1>;
144 #size-cells = <1>;
149 devbus-cs2 {
150 compatible = "marvell,mvebu-devbus";
153 #address-cells = <1>;
154 #size-cells = <1>;
159 devbus-cs3 {
160 compatible = "marvell,mvebu-devbus";
163 #address-cells = <1>;
164 #size-cells = <1>;
169 internal-regs {
170 compatible = "simple-bus";
171 u-boot,dm-pre-reloc;
172 #address-cells = <1>;
173 #size-cells = <1>;
176 L2: cache-controller@8000 {
177 compatible = "arm,pl310-cache";
179 cache-unified;
180 cache-level = <2>;
181 arm,double-linefill-incr = <1>;
182 arm,double-linefill-wrap = <0>;
183 arm,double-linefill = <1>;
184 prefetch-data = <1>;
188 compatible = "arm,cortex-a9-scu";
193 compatible = "arm,cortex-a9-twd-timer";
199 gic: interrupt-controller@d000 {
200 compatible = "arm,cortex-a9-gic";
201 #interrupt-cells = <3>;
202 #size-cells = <0>;
203 interrupt-controller;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "marvell,orion-mdio";
218 compatible = "marvell,armada-375-pp2";
224 clock-names = "pp_clk", "gop_clk";
229 port-id = <0>;
235 port-id = <1>;
241 compatible = "marvell,orion-rtc";
247 compatible = "marvell,armada-375-spi",
248 "marvell,orion-spi";
250 #address-cells = <1>;
251 #size-cells = <0>;
252 cell-index = <0>;
259 compatible = "marvell,armada-375-spi",
260 "marvell,orion-spi";
262 #address-cells = <1>;
263 #size-cells = <0>;
264 cell-index = <1>;
271 compatible = "marvell,mv64xxx-i2c";
273 #address-cells = <1>;
274 #size-cells = <0>;
276 timeout-ms = <1000>;
282 compatible = "marvell,mv64xxx-i2c";
284 #address-cells = <1>;
285 #size-cells = <0>;
287 timeout-ms = <1000>;
293 compatible = "snps,dw-apb-uart";
295 reg-shift = <2>;
297 reg-io-width = <1>;
303 compatible = "snps,dw-apb-uart";
305 reg-shift = <2>;
307 reg-io-width = <1>;
313 compatible = "marvell,mv88f6720-pinctrl";
316 i2c0_pins: i2c0-pins {
321 i2c1_pins: i2c1-pins {
326 nand_pins: nand-pins {
335 sdio_pins: sdio-pins {
341 spi0_pins: spi0-pins {
349 compatible = "marvell,orion-gpio";
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
363 compatible = "marvell,orion-gpio";
366 gpio-controller;
367 #gpio-cells = <2>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
377 compatible = "marvell,orion-gpio";
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
387 system-controller@18200 {
388 compatible = "marvell,armada-375-system-controller";
392 gateclk: clock-gating-control@18220 {
393 compatible = "marvell,armada-375-gating-clock";
396 #clock-cells = <1>;
399 usbcluster: usb-cluster@18400 {
400 compatible = "marvell,armada-375-usb-cluster";
402 #phy-cells = <1>;
405 mbusc: mbus-controller@20000 {
406 compatible = "marvell,mbus-controller";
410 mpic: interrupt-controller@20a00 {
413 #interrupt-cells = <1>;
414 #size-cells = <1>;
415 interrupt-controller;
416 msi-controller;
421 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
423 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
430 clock-names = "nbclk", "fixed";
434 compatible = "marvell,armada-375-wdt";
437 clock-names = "nbclk", "fixed";
441 compatible = "marvell,armada-370-cpu-reset";
445 coherency-fabric@21010 {
446 compatible = "marvell,armada-375-coherency-fabric";
451 compatible = "marvell,orion-ehci";
456 phy-names = "usb";
461 compatible = "marvell,orion-ehci";
469 compatible = "marvell,armada-375-xhci";
474 phy-names = "usb";
479 compatible = "marvell,orion-xor";
499 compatible = "marvell,orion-xor";
519 compatible = "marvell,armada-375-crypto";
521 reg-names = "regs";
526 clock-names = "cesa0", "cesa1",
528 marvell,crypto-srams = <&crypto_sram0>,
530 marvell,crypto-sram-size = <0x800>;
534 compatible = "marvell,orion-sata";
538 clock-names = "0", "1";
543 compatible = "marvell,armada370-nand";
545 #address-cells = <1>;
546 #size-cells = <1>;
553 compatible = "marvell,orion-sdio";
557 bus-width = <4>;
558 cap-sdio-irq;
559 cap-sd-highspeed;
560 cap-mmc-highspeed;
565 compatible = "marvell,armada375-thermal";
570 coreclk: mvebu-sar@e8204 {
571 compatible = "marvell,armada-375-core-clock";
573 #clock-cells = <1>;
576 coredivclk: corediv-clock@e8250 {
577 compatible = "marvell,armada-375-corediv-clock";
579 #clock-cells = <1>;
581 clock-output-names = "nand";
586 compatible = "marvell,armada-370-pcie";
590 #address-cells = <3>;
591 #size-cells = <2>;
593 msi-parent = <&mpic>;
594 bus-range = <0x00 0xff>;
606 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
608 #address-cells = <3>;
609 #size-cells = <2>;
610 #interrupt-cells = <1>;
613 bus-range = <0x00 0xff>;
614 interrupt-map-mask = <0 0 0 0>;
615 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
616 marvell,pcie-port = <0>;
617 marvell,pcie-lane = <0>;
624 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
626 #address-cells = <3>;
627 #size-cells = <2>;
628 #interrupt-cells = <1>;
631 bus-range = <0x00 0xff>;
632 interrupt-map-mask = <0 0 0 0>;
633 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
634 marvell,pcie-port = <0>;
635 marvell,pcie-lane = <1>;
642 crypto_sram0: sa-sram0 {
643 compatible = "mmio-sram";
646 #address-cells = <1>;
647 #size-cells = <1>;
651 crypto_sram1: sa-sram1 {
652 compatible = "mmio-sram";
655 #address-cells = <1>;
656 #size-cells = <1>;