arm/dts/am437x-gp-evm.dts

62 		pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
63 		brightness-levels = <0 51 53 56 62 75 101 152 255>;
67 	matrix_keypad: matrix_keypad@0 {
79 		linux,keymap = <0x00000201      /* P1 */
80 				0x00010202      /* P2 */
81 				0x01000067      /* UP */
82 				0x0101006a      /* RIGHT */
83 				0x02000069      /* LEFT */
84 				0x0201006c>;      /* DOWN */
92 		pinctrl-0 = <&lcd_pins>;
112 			hsync-active = <0>;
113 			vsync-active = <0>;
127 		#clock-cells = <0>;
136 	pinctrl-0 = <&wlan_pins_default>;
141 			0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
142 			0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
148 			0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
149 			0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
155 			0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
161 			0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
167 			0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
174 			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_txen */
175 			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rxctl */
176 			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd3 */
177 			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd2 */
178 			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd1 */
179 			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd0 */
180 			0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rmii1_tclk */
181 			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rmii1_rclk */
182 			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd3 */
183 			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd2 */
184 			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd1 */
185 			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd0 */
192 			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
193 			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
194 			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
195 			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
196 			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
197 			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
198 			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
199 			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
200 			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
201 			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
202 			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
203 			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
210 			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
211 			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
218 			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
219 			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
225 			0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* spi2_cs0.gpio/eMMCorNANDsel */
226 			0x0  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
227 			0x4  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
228 			0x8  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
229 			0xc  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
230 			0x10 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
231 			0x14 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
232 			0x18 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
233 			0x1c (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
234 			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
235 			0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
236 			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
237 			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
238 			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
239 			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
240 			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
246 			0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
247 			0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
248 			0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
249 			0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
250 			0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
251 			0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
252 			0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
253 			0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
254 			0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
255 			0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
256 			0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
257 			0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
258 			0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
259 			0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
260 			0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
261 			0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
262 			0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
263 			0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
264 			0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
265 			0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
266 			0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
267 			0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
268 			0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
269 			0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
270 			0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
271 			0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
272 			0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
273 			0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
281 			0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
287 			0x178 (PIN_OUTPUT | MUX_MODE2)		/* uart1_ctsn.d_can0_tx */
288 			0x17c (PIN_INPUT_PULLUP | MUX_MODE2)	/* uart1_rtsn.d_can0_rx */
294 			0x180 (PIN_OUTPUT | MUX_MODE2)		/* uart1_rxd.d_can1_tx */
295 			0x184 (PIN_INPUT_PULLUP | MUX_MODE2)	/* uart1_txd.d_can1_rx */
301 			0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
302 			0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
303 			0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
304 			0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
305 			0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
306 			0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
307 			0x20C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
308 			0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
309 			0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
310 			0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
311 			0x21C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
312 			0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
313 			0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
319 			0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
320 			0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
321 			0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
322 			0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
323 			0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
324 			0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
325 			0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
326 			0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
327 			0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
328 			0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
329 			0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
330 			0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
331 			0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
337 			0x1CC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
338 			0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
339 			0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
340 			0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
341 			0x1DC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
342 			0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
343 			0x1EC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
344 			0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
345 			0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
346 			0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
347 			0x1FC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
348 			0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
349 			0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
355 			0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
356 			0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
357 			0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
358 			0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
359 			0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
360 			0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
361 			0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
362 			0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
363 			0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
364 			0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
365 			0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
366 			0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
367 			0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
373 			0x8c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
374 			0x88 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
375 			0x44 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
376 			0x48 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
377 			0x4c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
378 			0x78 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
384 			0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_clk.mmc2_clk */
385 			0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_csn3.mmc2_cmd */
386 			0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a1.mmc2_dat0 */
387 			0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a2.mmc2_dat1 */
388 			0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a3.mmc2_dat2 */
389 			0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_be1n.mmc2_dat3 */
395 			0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a4.gpio1_20 WL_EN */
396 			0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)	/* gpmc_a7.gpio1_23 WL_IRQ*/
397 			0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a0.gpio1_16 BT_EN*/
403 			0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)		/* gpmc_a4.gpio1_20 WL_EN */
404 			0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)	/* gpmc_a7.gpio1_23 WL_IRQ*/
405 			0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7)		/* gpmc_a0.gpio1_16 BT_EN*/
411 			0x228 (PIN_INPUT | MUX_MODE0)		/* uart3_rxd.uart3_rxd */
412 			0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
413 			0x230 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart3_ctsn.uart3_ctsn */
414 			0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
422 	pinctrl-0 = <&i2c0_pins>;
426 		reg = <0x24>;
483 		reg = <0x30>;
485 		clocks = <&refclk 0>;
500 	pinctrl-0 = <&i2c1_pins>;
504 		pinctrl-0 = <&pixcir_ts_pins>;
505 		reg = <0x5c>;
507 		interrupts = <22 0>;
517 		reg = <0x30>;
519 		clocks = <&refclk 0>;
539 		ti,adc-channels = <0 1 2 3 4 5 6 7>;
546 	pinctrl-0 = <&ecap0_pins>;
575 	pinctrl-0 = <&mmc1_pins>;
590 	pinctrl-0 = <&mmc3_pins_default>;
597 	#size-cells = <0>;
598 	wlcore: wlcore@0 {
614 	pinctrl-0 = <&uart3_pins>;
638 	pinctrl-0 = <&cpsw_default>;
645 	pinctrl-0 = <&davinci_mdio_default>;
651 	phy_id = <&davinci_mdio>, <0>;
662 	pinctrl-0 = <&nand_flash_x8>;
663 	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
664 	nand@0,0 {
665 		reg = <0 0 4>;		/* device IO registers */
670 		gpmc,sync-clk-ps = <0>;
671 		gpmc,cs-on-ns = <0>;
674 		gpmc,adv-on-ns = <0>;
677 		gpmc,we-on-ns = <0>;
684 		gpmc,wait-pin = <0>;
685 		gpmc,bus-turnaround-ns = <0>;
686 		gpmc,cycle2cycle-delay-ns = <0>;
687 		gpmc,clk-activation-ns = <0>;
688 		gpmc,wait-monitoring-ns = <0>;
690 		gpmc,wr-data-mux-bus-ns = <0>;
697 		partition@0 {
699 			reg = <0x00000000 0x00040000>;
703 			reg = <0x00040000 0x00040000>;
707 			reg = <0x00080000 0x00040000>;
711 			reg = <0x000c0000 0x00040000>;
715 			reg = <0x00100000 0x00080000>;
719 			reg = <0x00180000 0x00100000>;
723 			reg = <0x00280000 0x00040000>;
727 			reg = <0x002c0000 0x00040000>;
731 			reg = <0x00300000 0x00700000>;
735 			reg = <0x00a00000 0x1f600000>;
744 	pinctrl-0 = <&dss_pins>;
747 		dpi_out: endpoint@0 {
756 	pinctrl-0 = <&dcan0_default>;
762 	pinctrl-0 = <&dcan1_default>;
769 	pinctrl-0 = <&vpfe0_pins_default>;
775 			ti,am437x-vpfe-interface = <0>;
777 			hsync-active = <0>;
778 			vsync-active = <0>;
786 	pinctrl-0 = <&vpfe1_pins_default>;
792 			ti,am437x-vpfe-interface = <0>;
794 			hsync-active = <0>;
795 			vsync-active = <0>;