16 struct hi6220_pinmux1_regs *pmx1 =  variable
26 		writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[49]); /* UART0_RXD */  in hi6220_uart_config()
27 		writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[50]); /* UART0_TXD */  in hi6220_uart_config()
36 		writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[51]); /*UART1_CTS_N*/  in hi6220_uart_config()
37 		writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[53]); /* UART1_RXD */  in hi6220_uart_config()
38 		writel(DRIVE1_02MA, &pmx1->iocfg[52]); /* UART1_RTS_N */  in hi6220_uart_config()
39 		writel(DRIVE1_02MA, &pmx1->iocfg[54]); /* UART1_TXD */  in hi6220_uart_config()
48 		writel(DRIVE1_02MA, &pmx1->iocfg[55]); /* UART2_CTS_N */  in hi6220_uart_config()
49 		writel(DRIVE1_02MA, &pmx1->iocfg[56]); /* UART2_RTS_N */  in hi6220_uart_config()
50 		writel(DRIVE1_02MA, &pmx1->iocfg[57]); /* UART2_RXD */  in hi6220_uart_config()
51 		writel(DRIVE1_02MA, &pmx1->iocfg[58]); /* UART2_TXD */  in hi6220_uart_config()
61 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[100]);  in hi6220_uart_config()
63 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[101]);  in hi6220_uart_config()
65 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[102]);  in hi6220_uart_config()
67 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[103]);  in hi6220_uart_config()
77 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[120]);  in hi6220_uart_config()
79 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[121]);  in hi6220_uart_config()
81 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[122]);  in hi6220_uart_config()
83 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[123]);  in hi6220_uart_config()
90 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[118]);  in hi6220_uart_config()
92 		writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[119]);  in hi6220_uart_config()
122 		writel(DRIVE1_08MA, &pmx1->iocfg[65]); /* EMMC_CLK */  in hi6220_mmc_config()
125 		writel(tmp, &pmx1->iocfg[65]); /* EMMC_CMD */  in hi6220_mmc_config()
126 		writel(tmp, &pmx1->iocfg[66]); /* EMMC_DATA0 */  in hi6220_mmc_config()
127 		writel(tmp, &pmx1->iocfg[67]); /* EMMC_DATA1 */  in hi6220_mmc_config()
128 		writel(tmp, &pmx1->iocfg[68]); /* EMMC_DATA2 */  in hi6220_mmc_config()
129 		writel(tmp, &pmx1->iocfg[69]); /* EMMC_DATA3 */  in hi6220_mmc_config()
130 		writel(tmp, &pmx1->iocfg[70]); /* EMMC_DATA4 */  in hi6220_mmc_config()
131 		writel(tmp, &pmx1->iocfg[71]); /* EMMC_DATA5 */  in hi6220_mmc_config()
132 		writel(tmp, &pmx1->iocfg[72]); /* EMMC_DATA6 */  in hi6220_mmc_config()
133 		writel(tmp, &pmx1->iocfg[73]); /* EMMC_DATA7 */  in hi6220_mmc_config()
135 		writel(DRIVE1_04MA, &pmx1->iocfg[73]); /* EMMC_RST_N */  in hi6220_mmc_config()
147 		writel(DRIVE1_10MA | BIT(2), &pmx1->iocfg[3]); /*SD_CLK*/  in hi6220_mmc_config()
148 		writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[4]); /*SD_CMD*/  in hi6220_mmc_config()
149 		writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[5]); /*SD_DATA0*/  in hi6220_mmc_config()
150 		writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[6]); /*SD_DATA1*/  in hi6220_mmc_config()
151 		writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[7]); /*SD_DATA2*/  in hi6220_mmc_config()
152 		writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[8]); /*SD_DATA3*/  in hi6220_mmc_config()