13 struct hi6220_pinmux0_regs *pmx0 =  variable
23 		writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */  in hi6220_uart_config()
24 		writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */  in hi6220_uart_config()
31 		writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */  in hi6220_uart_config()
32 		writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */  in hi6220_uart_config()
33 		writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */  in hi6220_uart_config()
34 		writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */  in hi6220_uart_config()
43 		writel(MUX_M0, &pmx0->iomg[54]); /* UART2_CTS_N */  in hi6220_uart_config()
44 		writel(MUX_M0, &pmx0->iomg[55]); /* UART2_RTS_N */  in hi6220_uart_config()
45 		writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */  in hi6220_uart_config()
46 		writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */  in hi6220_uart_config()
55 		writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */  in hi6220_uart_config()
56 		writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */  in hi6220_uart_config()
57 		writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */  in hi6220_uart_config()
58 		writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */  in hi6220_uart_config()
71 		writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */  in hi6220_uart_config()
72 		writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */  in hi6220_uart_config()
73 		writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */  in hi6220_uart_config()
74 		writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */  in hi6220_uart_config()
86 		writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */  in hi6220_uart_config()
87 		writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */  in hi6220_uart_config()
110 		writel(MUX_M0, &pmx0->iomg[64]); /* EMMC_CLK */  in hi6220_mmc_config()
111 		writel(MUX_M0, &pmx0->iomg[65]); /* EMMC_CMD */  in hi6220_mmc_config()
112 		writel(MUX_M0, &pmx0->iomg[66]); /* EMMC_DATA0 */  in hi6220_mmc_config()
113 		writel(MUX_M0, &pmx0->iomg[67]); /* EMMC_DATA1 */  in hi6220_mmc_config()
114 		writel(MUX_M0, &pmx0->iomg[68]); /* EMMC_DATA2 */  in hi6220_mmc_config()
115 		writel(MUX_M0, &pmx0->iomg[69]); /* EMMC_DATA3 */  in hi6220_mmc_config()
116 		writel(MUX_M0, &pmx0->iomg[70]); /* EMMC_DATA4 */  in hi6220_mmc_config()
117 		writel(MUX_M0, &pmx0->iomg[71]); /* EMMC_DATA5 */  in hi6220_mmc_config()
118 		writel(MUX_M0, &pmx0->iomg[72]); /* EMMC_DATA6 */  in hi6220_mmc_config()
119 		writel(MUX_M0, &pmx0->iomg[73]); /* EMMC_DATA7 */  in hi6220_mmc_config()
140 		writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */  in hi6220_mmc_config()
141 		writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */  in hi6220_mmc_config()
142 		writel(MUX_M0, &pmx0->iomg[5]); /* SD_DATA0 */  in hi6220_mmc_config()
143 		writel(MUX_M0, &pmx0->iomg[6]); /* SD_DATA1 */  in hi6220_mmc_config()
144 		writel(MUX_M0, &pmx0->iomg[7]); /* SD_DATA2 */  in hi6220_mmc_config()
145 		writel(MUX_M0, &pmx0->iomg[8]); /* SD_DATA3 */  in hi6220_mmc_config()