armv8/fsl-layerscape/lowlevel.S

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * (C) Copyright 2014-2015 Freescale Semiconductor
12 #include <asm/arch-fsl-layerscape/soc.h>
17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
19 #include <asm/u-boot.h>
36 	ldr     x2, =DCFG_CCSR_SVR
37 	ldr	w2, [x2]
46 	ldr	x2, =SCFG_GIC400_ALIGN
47 	ldr	w2, [x2]
88 	/* Set Wuo bit for RN-I 20 */
95 	 * Set forced-order mode in RNI-6, RNI-20
97 	 * LS2080A family does not support setting forced-order mode,
115 	/* Add fully-coherent masters to DVM domain */
118 	ldr	x2, =CCI_MN_DVM_DOMAIN_CTL_SET
121 	/* Set all RN-I ports to QoS of 15 */
219 	ldr	x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
239 	 * a. We use only Region0 whose global secure write/read is EN
240 	 * b. We use only Region0 whose NSAID write/read is EN
262 	ldr     w0, [x1]		/* Region-0 Attributes Register */
263 	orr     w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
264 	orr     w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
270 	ldr     w0, [x1]		/* Region-0 Access Register */
299 	orr   x1, x1, #0x2
329 	mov	x2, #0
331 	str	x2, [x0]
334 	b.lo	clear_loop
360 	 * clobber x1, x2, x3, x4, x6, x7
368 	mov	w6, #8			/* HN-F node count */
370 	ldr	x2, [x0]
371 	cmp	x2, x1			/* check status */
387 	/* x0 has the desired state, clobber x1, x2, x6 */
390 	mov	w6, #8			/* HN-F node count */
394 	ldr	x2, [x0]
395 	and	x2, x2, #0xfffffffffffffffc	/* & HNFPSTAT_MASK */
396 	orr	x2, x2, x1
397 	str	x2, [x0]
429 	add	x8, x8, #0x2
454 	 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
456 	 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
466 	 * until AFF2_CLUSTERID and AFF3 have non-zero values)
472 	ubfm	x2, x0, #0, #1
473 	orr	x10, x2, x1, lsl #2	/* x10 has LPID */
543 	ubfm	x2, x0, #0, #1
544 	orr	x10, x2, x1, lsl #2	/* x10 has LPID */
582 	.quad .-secondary_boot_code