Lines Matching full:-
2 # Copyright 2014-2015 Freescale Semiconductor
4 # SPDX-License-Identifier: GPL-2.0+
15 - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
16 - Region 2 is at 0x80_8000_0000 to the top of total memory,
19 All DDR memory is marked as cache-enabled.
27 +---------------+ <-- top/end of memory
29 +---------------+
31 +---------------+
42 pre-silicon platforms (simulator and emulator):
44 -------------------------
47 ------------------------- ----> 0x0120_0000
49 ------------------------- ----> 0x00C0_0000
51 ------------------------- ----> 0x0070_0000
53 ------------------------- ----> 0x006C_0000
55 ------------------------- ----> 0x0020_0000
57 ------------------------- ----> 0x0000_1000
59 ------------------------- ----> 0x0000_0080
61 ------------------------- ----> 0x0000_0000
63 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
68 ----------------------------------------- ----> 0x5_8800_0000 ---
70 ----------------------------------------- ----> 0x5_8790_0000 |
72 ----------------------------------------- ----> 0x5_8510_0000 |
74 ----------------------------------------- ----> 0x5_84F0_0000 | 64K
76 ----------------------------------------- ----> 0x5_84D0_0000 | Bank
78 ----------------------------------------- ----> 0x5_8490_0000 (vbank4)
80 ----------------------------------------- ----> 0x5_8480_0000 |
82 ----------------------------------------- ----> 0x5_8470_0000 |
84 ----------------------------------------- ----> 0x5_8430_0000 |
86 ----------------------------------------- ----> 0x5_8420_0000 |
88 ----------------------------------------- ----> 0x5_8410_0000 |
90 ----------------------------------------- ----> 0x5_8400_0000 ---
92 ----------------------------------------- ----> 0x5_8390_0000 |
94 ----------------------------------------- ----> 0x5_8110_0000 |
96 ----------------------------------------- ----> 0x5_80F0_0000 | 64K
98 ----------------------------------------- ----> 0x5_80D0_0000 |
100 ----------------------------------------- ----> 0x5_8090_0000 (vbank0)
102 ----------------------------------------- ----> 0x5_8080_0000 |
104 ----------------------------------------- ----> 0x5_8070_0000 |
106 ----------------------------------------- ----> 0x5_8030_0000 |
108 ----------------------------------------- ----> 0x5_8020_0000 |
110 ----------------------------------------- ----> 0x5_8010_0000 |
112 ----------------------------------------- ----> 0x5_8000_0000 ---
114 128-MB NOR flash layout for QDS and RDB boards
126 u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
128 during U-boot booting.However the MC, DPC and DPL can be applied from
154 -------------------
155 Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
160 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
161 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
163 the u-boot code will be running in OCRAM.
167 This command copies u-boot image from NAND device into OCRAM. The values need
172 SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In
179 u-boot command
183 To form the NAND image, build u-boot with NAND config, for example,
184 ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
185 The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
187 nand write <u-boot image in memory> 200000 <size of u-boot image>
193 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
194 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
199 nand write <u-boot image in memory> 80000 <size of u-boot image>
201 Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
207 -------------------
208 Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin.
209 The difference between SD boot RCW image and QSPI-NOR boot image is the
217 This command copies u-boot image from SD device into OCRAM. The values
223 SRC_ADDR is the offset of u-boot-with-spl.bin image in SD device.
224 In the example above, 1MB. This is same as QSPI-NOR.
228 2) CCSR 4-byte write to 0x01e00404, data=0x00000000
229 3) CCSR 4-byte write to 0x01e00400, data=0x1800a000
231 the u-boot code will be running in OCRAM.
235 using u-boot command
240 To form the SD-Boot image, build u-boot with SD config, for example,
241 ls1088ardb_sdcard_qspi_defconfig. The image needed is u-boot-with-spl.bin.
242 The u-boot image should be written to match SRC_ADDR, in above example
246 mmc write <u-boot image in memory> 0x800 <size of u-boot image in block count>
256 ------------------ ------------------ ------------------
257 | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
258 ------------------ ------------------ ------------------
259 | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
260 ------------------ | ------------------ ------------------
262 ------------------ | ------------------ ------------------
264 | ------------------ ------------------
266 | ------------------ ------------------
268 | ------------------
269 | | 0x05_8000_0000 | --|
270 | ------------------ |
272 | ------------------ |
274 | ------------------ | ------------------
275 |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 |
276 ------------------ ------------------
278 ------------------ ------------------
280 ------------------ ------------------
282 ------------------ ------------------
284 ------------------ ------------------
290 ------------------ ------------------ ------------------
291 | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
292 ------------------ ------------------ ------------------
293 | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
294 ------------------ | ------------------ ------------------
296 ------------------ | ------------------ ------------------
298 | ------------------ ------------------
300 | ------------------ ------------------
302 | ------------------
303 | | 0x08_0000_0000 | --|
304 | ------------------ |
306 | ------------------ |
308 | ------------------ | ------------------
309 |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 |
310 ------------------ ------------------
312 ------------------ ------------------
314 ------------------ ------------------
316 ------------------ ------------------
318 ------------------ ------------------
323 ------------------------------------------------
326 from u-boot command prompt.
329 more deployed during u-boot boot-sequence.
332 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
333 b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
334 c) fsl_mc start aiop <FW_addr> - Start AIOP
336 How to use commands :-
337 1. Command sequence for u-boot ethernet:
338 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
339 b) DPMAC net-devices are now available for use
341 Example-
350 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
351 b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
352 c) No DPMAC net-devices are available for use in u-boot
355 Example-
366 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
367 b) fsl_mc start aiop <FW_addr> - Start AIOP
368 c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
369 d) No DPMAC net-devices are availabe for use in u-boot
373 Example-
383 ---------------
394 - Default value of env variable is platform clock (MHz)
396 - User can modify default value by updating the env variable
400 - Env variable as 0 signifies no workaround