1 // SPDX-License-Identifier: GPL-2.0+
5  * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
32 	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);  in ls1_save_ddr_head()
36 	out_le32(&scfg->sparecr[2], dest);  in ls1_save_ddr_head()
52 	/* Pull MCKE signal low before enabling deep sleep signal in FPGA */  in ls1_fsm_setup()
64 	out_be32(&rcpm->nfiqoutr, 0x0ffffffff);  in ls1_deepsleep_irq_cfg()
65 	out_be32(&rcpm->nirqoutr, 0x0ffffffff);  in ls1_deepsleep_irq_cfg()
66 	/* Mask deep sleep wake-up interrupts while entering deep sleep */  in ls1_deepsleep_irq_cfg()
67 	out_be32(&rcpm->dsimskr, 0x0ffffffff);  in ls1_deepsleep_irq_cfg()
69 	ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);  in ls1_deepsleep_irq_cfg()
75 	ippdexpcr1 = in_le32(&scfg->sparecr[7]);  in ls1_deepsleep_irq_cfg()
76 	out_be32(&rcpm->ippdexpcr1, ippdexpcr1);  in ls1_deepsleep_irq_cfg()
96 	out_be32(&scfg->pmcintlecr, 0);  in ls1_deepsleep_irq_cfg()
98 	out_be32(&scfg->pmcintsr, 0xffffffff);  in ls1_deepsleep_irq_cfg()
99 	/* Enable wakeup interrupt during deep sleep */  in ls1_deepsleep_irq_cfg()
100 	out_be32(&scfg->pmcintecr, pmcintecr);  in ls1_deepsleep_irq_cfg()
105 	while (loop--) {  in ls1_delay()
107 		while (i--)  in ls1_delay()
120 	setbits_be32(&scfg->hrstcr, 0x80000000);  in ls1_start_fsm()
123 	setbits_be32(&ddr->sdram_cfg_2, 0x80000000);  in ls1_start_fsm()
160 	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);  in ls1_deep_sleep()
166 	out_le32(&scfg->sparecr[3], entry_point);  in ls1_deep_sleep()
169 	setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);  in ls1_deep_sleep()
171 	/* Setup the registers of the EPU FSM for deep sleep */  in ls1_deep_sleep()
181 	/* Enable deep sleep signals in FPGA */  in ls1_deep_sleep()
193 	setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);  in ls1_deep_sleep()
194 	setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);  in ls1_deep_sleep()
197 	setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE);  in ls1_deep_sleep()
224 	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);  in ls1_sleep()
226 	setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);  in ls1_sleep()