armv7/ls102xa/cpu.c

1 // SPDX-License-Identifier: GPL-2.0+
120  * The base address of TTLB is gd->arch.tlb_addr. We use two
121  * levels of translation tables here to cover 40-bit address space.
127  *  -------  <---- 0GB
130  * |-------| <---- 0x24000000
131  * |///////|  ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
132  * |-------| <---- 0x300000000
134  * |-------| <---- 0x34000000
136  * |-------| <---- 0x40000000
138  * |-------| <---- 0x80000000 DDR0 space start
142  *  -------  <---- 4GB DDR0 space end
146 	u32 *level0_table = (u32 *)gd->arch.tlb_addr;  in mmu_setup()
147 	u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);  in mmu_setup()
152 	/* Level 0 Table 2-3 are used to map DDR */  in mmu_setup()
193 	/* Set the access control to all-supervisor */  in mmu_setup()
204  * table in main memory. MMU and i/d-cache are enabled here.
209 	mmu_page_table_flush(gd->arch.tlb_addr,  in enable_caches()
210 			     gd->arch.tlb_addr +  gd->arch.tlb_size);  in enable_caches()
214 	/* Invalidate & Enable d-cache */  in enable_caches()
225 	return in_be32(&gur->svr);  in get_svr()
235 	svr = in_be32(&gur->svr);  in print_cpuinfo()
255 	default:  in print_cpuinfo()
267 	printf("\n       CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));  in print_cpuinfo()
268 	printf("\n       Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));  in print_cpuinfo()
269 	printf("DDR:%-4s MHz (%s MT/s data rate), ",  in print_cpuinfo()
270 	       strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));  in print_cpuinfo()
277 	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {  in print_cpuinfo()
278 		u32 rcw = in_be32(&gur->rcwsr[i]);  in print_cpuinfo()
312 	u32 state;  in arch_cpu_init()  local
315 	 * The RCPM FSM state may not be reset after power-on.  in arch_cpu_init()
318 	state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &  in arch_cpu_init()
320 	if (state != 0) {  in arch_cpu_init()
325 	state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &  in arch_cpu_init()
327 	if (state != 0) {  in arch_cpu_init()
339 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);  in arch_cpu_init()
350 	out_be32(&gur->scratchrw[0], addr);  in smp_set_core_boot_addr()
353 /* Release the secondary core from holdoff state and kick it */
358 	out_be32(&gur->brrl, 0x2);  in smp_kick_all_cpus()
374 	clrbits_be16(&wdog->wcr, WCR_SRS);  in reset_cpu()