32 	u32 ddr1v8, ddr2v5;  in sel_1v8()  local
34 	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);  in sel_1v8()
35 	ddr2v5 &= 0x8080ffc0;  in sel_1v8()
36 	ddr2v5 |= 0x78000003;  in sel_1v8()
37 	writel(ddr2v5, &misc_p->ddr_2v5_compensation);  in sel_1v8()
51 	u32 ddr1v8, ddr2v5;  in sel_2v5()  local
58 	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);  in sel_2v5()
59 	ddr2v5 &= 0x8080ffc0;  in sel_2v5()
60 	ddr2v5 |= 0x78000010;  in sel_2v5()
61 	writel(ddr2v5, &misc_p->ddr_2v5_compensation);  in sel_2v5()
74 	u32 core3v3, ddr1v8, ddr2v5;  in plat_ddr_init()  local
100 	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);  in plat_ddr_init()
101 	ddr2v5 &= 0x8080ffc0;  in plat_ddr_init()
102 	ddr2v5 |= 0x78000004;  in plat_ddr_init()
103 	writel(ddr2v5, &misc_p->ddr_2v5_compensation);  in plat_ddr_init()