1 // SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/imx-regs.h>
21  *   iMX28: datasheet section 10.2
44 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);  in mxs_get_pclk()
52 	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);  in mxs_get_pclk()
62 	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);  in mxs_get_pclk()
76 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);  in mxs_get_hclk()
94 	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);  in mxs_get_emiclk()
95 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);  in mxs_get_emiclk()
105 	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);  in mxs_get_emiclk()
117 		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];  in mxs_get_gpmiclk()
120 		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];  in mxs_get_gpmiclk()
125 	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);  in mxs_get_gpmiclk()
126 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);  in mxs_get_gpmiclk()
165 	io_reg = CLKCTRL_FRAC0_IO0 - io;	/* Register order is reversed */  in mxs_set_ioclk()
167 		&clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);  in mxs_set_ioclk()
169 		&clkctrl_regs->hw_clkctrl_frac0[io_reg]);  in mxs_set_ioclk()
171 		&clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);  in mxs_set_ioclk()
187 	io_reg = CLKCTRL_FRAC0_IO0 - io;	/* Register order is reversed */  in mxs_get_ioclk()
189 	ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &  in mxs_get_ioclk()
207 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +  in mxs_set_sspclk()
233 			&clkctrl_regs->hw_clkctrl_clkseq_set);  in mxs_set_sspclk()
236 			&clkctrl_regs->hw_clkctrl_clkseq_clr);  in mxs_set_sspclk()
252 	tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);  in mxs_get_sspclk()
256 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +  in mxs_get_sspclk()
270  * Set SSP/MMC bus frequency, in kHz)
304 		((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);  in mxs_set_ssp_busclock()
305 	writel(reg, &ssp_regs->hw_ssp_timing);  in mxs_set_ssp_busclock()
322 	writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);  in mxs_set_lcdclk()
324 	writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);  in mxs_set_lcdclk()
329 	 * freq kHz = | 480000000 Hz * --  | * --- * ------  in mxs_set_lcdclk()
333 	 *      ------------ * --  in mxs_set_lcdclk()
335 	 * k = -------------------  in mxs_set_lcdclk()
359 	if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {  in mxs_set_lcdclk()
371 		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);  in mxs_set_lcdclk()
373 		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);  in mxs_set_lcdclk()
375 		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);  in mxs_set_lcdclk()
378 		&clkctrl_regs->hw_clkctrl_pix_set);  in mxs_set_lcdclk()
379 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,  in mxs_set_lcdclk()
383 	while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)  in mxs_set_lcdclk()
387 		&clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);  in mxs_set_lcdclk()
389 		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);  in mxs_set_lcdclk()
391 		&clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);  in mxs_set_lcdclk()
394 		&clkctrl_regs->hw_clkctrl_lcdif_set);  in mxs_set_lcdclk()
395 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,  in mxs_set_lcdclk()
399 	while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)  in mxs_set_lcdclk()