1 // SPDX-License-Identifier: GPL-2.0+
6  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
18 #include <asm/arch/emc.h>
22 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;  variable
28 	/* Enable EMC interface and choose little endian mode */  in ddr_init()
29 	writel(1, &emc->ctrl);  in ddr_init()
30 	writel(0, &emc->config);  in ddr_init()
31 	/* Select maximum EMC Dynamic Memory Refresh Time */  in ddr_init()
32 	writel(0x7FF, &emc->refresh);  in ddr_init()
36 	writel(dram->cmddelay, &clk->sdramclk_ctrl);  in ddr_init()
37 	writel(dram->config0, &emc->config0);  in ddr_init()
38 	writel(dram->rascas0, &emc->rascas0);  in ddr_init()
39 	writel(dram->rdconfig, &emc->read_config);  in ddr_init()
41 	writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);  in ddr_init()
42 	writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);  in ddr_init()
43 	writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);  in ddr_init()
44 	writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);  in ddr_init()
45 	writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);  in ddr_init()
46 	writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);  in ddr_init()
47 	writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);  in ddr_init()
48 	writel(dram->trrd, &emc->t_rrd);  in ddr_init()
49 	writel(dram->tmrd, &emc->t_mrd);  in ddr_init()
50 	writel(dram->tcdlr, &emc->t_cdlr);  in ddr_init()
52 	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);  in ddr_init()
55 	writel(0x00000193, &emc->control);  in ddr_init()
58 	writel(0x00000113, &emc->control);  in ddr_init()
60 	writel((((128) >> 4) & 0x7FF), &emc->refresh);  in ddr_init()
63 	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);  in ddr_init()
65 	/* set normal mode to CAS=3 */  in ddr_init()
66 	writel(0x00000093, &emc->control);  in ddr_init()
67 	readl(EMC_DYCS0_BASE | dram->mode);  in ddr_init()
68 	/* set extended mode to all zeroes */  in ddr_init()
69 	writel(0x00000093, &emc->control);  in ddr_init()
70 	readl(EMC_DYCS0_BASE | dram->emode);  in ddr_init()
71 	/* stop forcing clocks, keep inverted clock, issue normal mode */  in ddr_init()
72 	writel(0x00000010, &emc->control);  in ddr_init()