Lines Matching +full:0 +full:xda

12 #define ESDCTL_DDR2_EMR2	0x04000000
13 #define ESDCTL_DDR2_EMR3	0x06000000
14 #define ESDCTL_PRECHARGE	0x00000400
15 #define ESDCTL_DDR2_EN_DLL	0x02000400
16 #define ESDCTL_DDR2_RESET_DLL	0x00000333
17 #define ESDCTL_DDR2_MR		0x00000233
18 #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
21 	SMODE_NORMAL =	0,
76 	dram_wait(0x20000);  in mx3_setup_sdram_bank()
84 	writel(0xda, start_address + ESDCTL_PRECHARGE);  in mx3_setup_sdram_bank()
89 	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */  in mx3_setup_sdram_bank()
90 	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */  in mx3_setup_sdram_bank()
91 	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */  in mx3_setup_sdram_bank()
92 	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */  in mx3_setup_sdram_bank()
97 	writel(0xda, start_address + ESDCTL_PRECHARGE);  in mx3_setup_sdram_bank()
102 	writel(0xda, start_address);  in mx3_setup_sdram_bank()
103 	writel(0xda, start_address);  in mx3_setup_sdram_bank()
107 	writeb(0xda, start_address + ESDCTL_DDR2_MR);  in mx3_setup_sdram_bank()
108 	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);  in mx3_setup_sdram_bank()
111 	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */  in mx3_setup_sdram_bank()
117 	dram_wait(0x20000);  in mx3_setup_sdram_bank()